The EF_ADCS0801 is a low-power, single-channel CMOS 8-bit analogue-to-digital converter with a flexible parallel interface. Moreover, start-of-conversion (SOC) and end-of-conversion (EOC) terminals facilitate the sample rate operating range. The converter is based on a successive approximation register (SAR) architecture with an internal track-and-hold circuit. It can be configured to accept a 2.5 V single-ended input span. The output parallel data is binary and compatible with many common DSP parallel interfaces. The EF_ADCS0801 operates with a dual power supply; 1.8 V and 3.3 V supply the digital and analog IP blocks, respectively. Normal power consumption reaches 0.92 mW in idle mode. The functional block diagram is presented in Figure 1.
Figure 1. Functional Block Diagram
Table 1. Pin Configuration and Functions
Table 2. Timing Paramters
Figure 2. Timing Diagram
The post-layout simulation results of the proposed EF_ADCS0801 are listed in Table 3. Those parameters are reported at Temp.=27°C, VDD of 3.3V, and DVDD of 1.8V, EN=1.8V, VH=2.5 V,and VL=0V.
Table 3. Electrical Characteristics
The proposed EF_ADCS0801 has been designed and simulated using open-source tools with SkyWater technology. Herein, XSCHEM is a schematic capture program that provides a graphical method of the electronic schematic circuit, easily. NGSPICE is an open-source spice simulator. It is exploited to simulate and verify the designed circuit. The layout of the EF_ADCS0801 is implemented using MAGIC 8.3 and for design rule check (DRC) as well. However, NETGEN is used for comparing netlists of the layout and schematic, known as layout vs schematic (LVS). PYTHON can be integrated with the NGSPICE simulator for data manipulation/analysis of the simulation result.
Next, typical performance curves of the EF_ADCS0801 post-layout simulations are presented. As presented in Figure 3, dynamic parameters of EF_ADCS0801 are calculated at CLK of 1 MHz and 2 MHz using a developed script.
Figure 3. Dynamic Parameters
Figure 4. Constructed signal and its spectrum at CLK=2MHz.
Figure 5. Constructed signal and its spectrum at CLK=1MHz.
Figure 6. EF_ADCS0801’s Layout
The files from this repository can be downloaded and used by the following commands:-
sudo apt install -y git
git clone https://github.com/efabless/EF_ADCS0801.git
EF_ADCS0801
Vendor
Efabless
130nm
Skywater
A/D Converter
Open Source (Free)
Uncertified
Characterized