The low power embedded display port PHY has been developed for eDP-TCON SoCs to be used for Chip on Glass (COG) applications at speeds up to 2.7 Gb/s data rates. The robust design is capable to withstand 120 mV voltage drop and 100 mV pk-pk power supply noise typically seen on COG applications. Programmable receiver equalization adaptively corrects the signal distortions caused in eDP cable and connector assembly. Built in self-test features offer at speed testing for mass production, functional and performance diagnostics as well as silicon characterization in the lab. The PHY is designed for UMCs 80nm CMOS process and uses only five metal layers.