The SYMLVDS33_A1 is a 630Mbps LVDS Transceiver that operates from supply voltage

of 1.2V and 3.3V. The IP uses the Altis ATS-130-RF, 130nm CMOS technology and is compatible with the ATS-130-LP process.

Both the LVDS transmitter and receiver can be powered down by asserting the PD pins high. The receiver has an optional internal on-chip termination and no internal clock or CDR allowing a very small and compact form factor to be achieved. Fail-safe circuitry is included in the receiver to cope with open circuit conditions when the driver is in a high impedance state or the cable is disconnected from the receiver. No external compensation is needed.

The LVDS transceiver is compliant with TIA/EIA-644A standard for point-to-point configuration as well as multi-drop configuration (up to 32 parallel connected receivers).