| ❗ Important Note |
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This is the EE372 VLSI Design Project at Stanford University. The chip is an incremental Delta-Sigma ADC in Skywater 130 nm CMOS technology.
This repo is the top-level wrapper for the design in order to participate in the Efabless 2206Q Tapeout Shuttle
| Use this sample project for analog user projects. |
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Refer to README for this sample project documentation.