• 1.RISC-V RV32I
• 2.BLOCK DIAGRAM OF RISC-V RV32I
• 3.INSTRUCTION SET OF RISC-V RV32I
• 4.FUNCTIONAL SIMULATION
  • 4.1 About iverilog and gtkwave
  • 4.2 Installing iverilog and gtkwave
  • 4.3 The output waveform
• 5.SYNTHESIS
  • 5.1 Synthesis
  • 5.2 Synthesizer
• 6.GATE LEVEL SIMULATION
• 7.PHYSICAL DESIGN
  • 7.1 Overview of Physical Design flow
  • 7.2 Openlane
  • 7.3 Installation Instructions
  • 7.4 Magic
  • 7.5 Generating Layout
  • 7.6 Customizing the layout

This project provides an insight into the working of a few important instructions of the instruction set of a Single cycle Reduced Instruction Set Computer - Five(RISC-V) Instruction Set Architecture suitable for use across wide-spectrum of Applications from low power embedded devices to high performance Cloud based Server processors. The base RISC-V is a 32-bit processor with 31 general-purpose registers, so all the instructions are 32-bit long. Some Applications where the RISC-V processors have begun to make some significant threads are in Artificial intelligence and machine learning, Embedded systems, Ultra Low power processing systems etc.

• Icarus Verilog is an implementation of the Verilog hardware description language.
• GTKWave is a fully featured GTK+ v1. 2 based wave viewer for Unix and Win32 which reads Ver Structural Verilog Compiler generated AET files as well as standard Verilog VCD/EVCD files and allows their viewing.

• For Ubuntu

Open your terminal and type the following to install iverilog and GTKWave

$   sudo apt get update
$   sudo apt get install iverilog gtkwave

• To clone the repository and download the netlist files for simulation , enter the following commands in your terminal.

$ git clone https://github.com/vinayrayapati/iiitb_rv32i
$ cd iiitb_rv32i

• To simulate and run the verilog code , enter the following commands in your terminal.

$ iverilog -o iiitb_rv32i iiitb_rv32i.v iiitb_rv32i_tb.v
$ ./iiitb_rv32i

• To see the output waveform in gtkwave, enter the following commands in your terminal.

$ gtkwave iiitb_rv32i.vcd

The output waveform showing the instructions performed in a 5-stage pipelined architecture.

Instruction 1:add r6,r2,r1

Instruction 2:sub r7,r1,r2

Instruction 3:and r8,r1,r3

Instruction 4:or r9,r2,r5

Instruction 5:xor r10,r1,r4

Instruction 6:slt r11,r2,r4

Instruction 7:addi r12,r4,5

Instruction 8:sw r3,r1,2

Instruction 9:lw r13,r1,2

Instruction 10:beq r0,r0,15

After branching, performing Instruction 11:add r14,r2,r2

Instruction 12:bne r0,r1,20

After branching, performing Instruction 13:addi r12,r4,5

Instruction 14:sll r15,r1,r2(2)

Instruction 15:srl r16,r14,r2(2)

Full 5-stage instruction pipeline and pc-increment description Waveform

Synthesis transforms the simple RTL design into a gate-level netlist with all the constraints as specified by the designer. In simple language, Synthesis is a process that converts the abstract form of design to a properly implemented chip in terms of logic gates.

Synthesis takes place in multiple steps:

• Converting RTL into simple logic gates.
• Mapping those gates to actual technology-dependent logic gates available in the technology libraries.
• Optimizing the mapped netlist keeping the constraints set by the designer intact.

It is a tool we use to convert out RTL design code to netlist. Yosys is the tool I've used in this project.

The commands to get the yosys is given belw:

git clone https://github.com/YosysHQ/yosys.git
make
sudo make install make test

Now you need to create a yosys_run.sh file , which is the yosys script file used to run the synthesis. The contents of the yosys_run file are given below:

read_liberty -lib lib/sky130_fd_sc_hd__tt_025C_1v80.lib
read_verilog iiitb_rv32i.v
synth -top iiitb_rv32i	
dfflibmap -liberty lib/sky130_fd_sc_hd__tt_025C_1v80.lib
proc ; opt
abc -liberty lib/sky130_fd_sc_hd__tt_025C_1v80.lib
clean
flatten
write_verilog -noattr iiitb_rv32i_synth.v

Now, in the terminal of your verilog files folder, run the following commands:

yosys
script yosys_run.sh

Now the synthesized netlist is written in "iiitb_rv32i_synth.v" file.

GLS is generating the simulation output by running test bench with netlist file generated from synthesis as design under test. Netlist is logically same as RTL code, therefore, same test bench can be used for it.We perform this to verify logical correctness of the design after synthesizing it. Also ensuring the timing of the design is met. Folllowing are the commands to run the GLS simulation:

iverilog -DFUNCTIONAL -DUNIT_DELAY=#1 ../verilog_model/primitives.v ../verilog_model/sky130_fd_sc_hd.v iiitb_rv32i_synth.v iiitb_rv32i_tb.v
./a.out
gtkwave iiitb_rv32i.vcd

The gtkwave output for the netlist should match the output waveform for the RTL design file. As netlist and design code have same set of inputs and outputs, we can use the same testbench and compare the waveforms.

The output waveform of the synthesized netlist given below:

Place and Route (PnR) is the core of any ASIC implementation and Openlane flow integrates into it several key open source tools which perform each of the respective stages of PnR. Below are the stages and the respective tools that are called by openlane for the functionalities as described:

• Synthesis
  • Generating gate-level netlist (yosys).
  • Performing cell mapping (abc).
  • Performing pre-layout STA (OpenSTA).
• Floorplanning
  • Defining the core area for the macro as well as the cell sites and the tracks (init_fp).
  • Placing the macro input and output ports (ioplacer).
  • Generating the power distribution network (pdn).
• Placement
  • Performing global placement (RePLace).
  • Perfroming detailed placement to legalize the globally placed components (OpenDP).
• Clock Tree Synthesis (CTS)
  • Synthesizing the clock tree (TritonCTS).
• Routing
  • Performing global routing to generate a guide file for the detailed router (FastRoute).
  • Performing detailed routing (TritonRoute)
• GDSII Generation
  • Streaming out the final GDSII layout file from the routed def (Magic).

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, CVC, SPEF-Extractor, CU-GR, Klayout and a number of custom scripts for design exploration and optimization. The flow performs full ASIC implementation steps from RTL all the way down to GDSII.

More about Openlane at : https://github.com/The-OpenROAD-Project/OpenLane

$   apt install -y build-essential python3 python3-venv python3-pip

Docker installation process: https://docs.docker.com/engine/install/ubuntu/

goto home directory->

$   git clone https://github.com/The-OpenROAD-Project/OpenLane.git
$   cd OpenLane/
$   sudo make

To test the open lane

$ sudo make test

It takes approximate time of 5min to complete. After 43 steps, if it ended with saying Basic test passed then open lane installed succesfully.

Magic is a venerable VLSI layout tool, written in the 1980's at Berkeley by John Ousterhout, now famous primarily for writing the scripting interpreter language Tcl. Due largely in part to its liberal Berkeley open-source license, magic has remained popular with universities and small companies. The open-source license has allowed VLSI engineers with a bent toward programming to implement clever ideas and help magic stay abreast of fabrication technology. However, it is the well thought-out core algorithms which lend to magic the greatest part of its popularity. Magic is widely cited as being the easiest tool to use for circuit layout, even for people who ultimately rely on commercial tools for their product design flow.

More about magic at http://opencircuitdesign.com/magic/index.html

Run following commands one by one to fulfill the system requirement.

$   sudo apt-get install m4
$   sudo apt-get install tcsh
$   sudo apt-get install csh
$   sudo apt-get install libx11-dev
$   sudo apt-get install tcl-dev tk-dev
$   sudo apt-get install libcairo2-dev
$   sudo apt-get install mesa-common-dev libglu1-mesa-dev
$   sudo apt-get install libncurses-dev

To install magic goto home directory

$   git clone https://github.com/RTimothyEdwards/magic
$   cd magic/
$   ./configure
$   sudo make
$   sudo make install

type magic terminal to check whether it installed succesfully or not. type exit to exit magic.

NON-INTERACTIVE MODE Here we are generating the layout in the non-interactive mode or the automatic mode. In this we cant interact with the flow in the middle of each stage of the flow.The flow completes all the stages starting from synthesis until you obtain the final layout and the reports of various stages which specify the violations and problems if present during the flow.

• Open terminal in home directory

  $   cd OpenLane/
  $   cd designs/
  $   mkdir iiitb_iiitb_rv32i
  $   cd iiitb_iiitb_rv32i/
  $   wget https://raw.githubusercontent.com/vinayrayapati/iiitb_rv32i/main/config.json
  $   mkdir src
  $   cd src/
  $   wget https://raw.githubusercontent.com/vinayrayapati/iiitb_rv32i/main/iiitb_rv32i.v
  $   cd ../../../
  $   sudo make mount
  $   ./flow.tcl -design iiitb_rv32i
  

• To see the layout we use a tool called magic which we installed earlier.Type the following command in the terminal opened in the path to your design/runs/latest run folder/final/def/

  $   magic -T /home/parallels/Desktop/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../../tmp/merged.max.lef def read iiitb_rv32i.def &
  

• The final layout obtained after the completion of the flow in non-interactive mode is shown below:

  

Here we are going to customise our layout by including our custom made sky130_vsdinv cell into our layout.

• 1 . CREATING THE SKY130_VSDINV CELL LEF FILE

  • You need to first get the git repository of the vsdstdccelldesign.To get the repository type the following command:

    git clone https://github.com/nickson-jose/vsdstdcelldesign.git

  • Now you need to copy your tech file sky130A.tech to this folder.

  • Next run the magic command to open the sky130_vsdinv.mag file.Use the following command:

    magic -T sky130A.tech sky130_vsdinv.mag&

    • One can zoom into Magic layout by selecting an area with left and right mouse click followed by pressing "z" key.
    • Various components can be identified by using the what command in tkcon window after making a selection on the component.

  • The image showing the invoked magic tool using the above command:

    

  • The next step is setting port class and port use attributes. The "class" and "use" properties of the port have no internal meaning to magic but are used by the LEF and DEF format read and write routines, and match the LEF/DEF CLASS and USE properties for macro cell pins. These attributes are set in tkcon window (after selecting each port on layout window. A keyboard shortcut would be,repeatedly pressing s till that port gets highlighed).

  • The tkcon command window of the port classification is shown in the image below:

    

  • In the next step, use lef write command to write the LEF file with the same nomenclature as that of the layout .mag file. This will create a sky130_vsdinv.lef file in the same folder.

    

• 2 . INCLUDING THE SKY130_VSDINV CELL

  • You need to copy the lib files and the created sky130_vsinv.lef file to your design src directory.The src directory image with its contents is shown below:

    

  • Next , Modify the json file by including the following lines:

    "PL_RANDOM_GLB_PLACEMENT": 1,
    "PL_TARGET_DENSITY": 0.5,
    "FP_SIZING": "relative",
    "LIB_SYNTH":"dir::src/sky130_fd_sc_hd__typical.lib",
    "LIB_FASTEST":"dir::src/sky130_fd_sc_hd__fast.lib",
    "LIB_SLOWEST":"dir::src/sky130_fd_sc_hd__slow.lib",
    "LIB_TYPICAL":"dir::src/sky130_fd_sc_hd__typical.lib",
    "TEST_EXTERNAL_GLOB":"dir::../iiitb_rv32i/src/*",
    "SYNTH_DRIVING_CELL":"sky130_vsdinv"
    

• 3 . INTERACTIVE MODE: We need to run the openlane now in the interactive mode to include our custom made lef file before synthesis.Such that the openlane recognises our lef files during the flow for mapping.

  • 1. Running openlane in interactive mode: The commands to the run the flow in interactive mode is given below:

    cd OpenLane
    sudo make mount
    ./flow.tcl -interactive
    

    

  • 2. Preparing the design and including the lef files: The commands to prepare the design and overwite in a existing run folder the reports and results along with the command to include the lef files is given below:

    prep -design iiitb_rv32i -tag run -overwrite
    set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
    add_lefs -src $lefs
    

    

• 4 . SYNTHESIS:

  • 1. The command to run the synthesis is run_synthesis.This runs the synthesis where yosys translates RTL into circuit using generic components and abc maps the circuit to Standard Cells.

  • 2. The synthesized netlist is present in the results folder and the stats are present in the reports folder as shown below:

    

  • 3. Calcuation of Flop Ratio:

    
    Flop ratio = Number of D Flip flops 
                 ______________________
                 Total Number of cells
    
    

  • 4. The slack report including the sky130_vsdinv cell is shown below:

    

• 5 . FLOORPLAN

  • 1. Importance of files in increasing priority order:

    1. floorplan.tcl - System default envrionment variables
    2. conifg.tcl
    3. sky130A_sky130_fd_sc_hd_config.tcl

  • 2. Floorplan envrionment variables or switches:

    1. FP_CORE_UTIL - floorplan core utilisation
    2. FP_ASPECT_RATIO - floorplan aspect ratio
    3. FP_CORE_MARGIN - Core to die margin area
    4. FP_IO_MODE - defines pin configurations (1 = equidistant/0 = not equidistant)
    5. FP_CORE_VMETAL - vertical metal layer
    6. FP_CORE_HMETAL - horizontal metal layer

    Note: Usually, vertical metal layer and horizontal metal layer values will be 1 more than that specified in the file

  • 3. To run the Floorplan use the command: run_floorplan.

  • 4. Post the floorplan run, a .def file will have been created within the results/floorplan directory. We may review floorplan files by checking the floorplan.tcl. The system defaults will have been overriden by switches set in conifg.tcl and further overriden by switches set in sky130A_sky130_fd_sc_hd_config.tcl.

  • 5. To view the floorplan: Magic is invoked after moving to the results/floorplan directory,then use the floowing command:

    magic -T /home/vinay/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.nom.lef def read iiitb_rv32i.def &
    

    

  • 6. Die Area post floorplan:

    

• 6 . PLACEMENT

  • 1. The next step in the OpenLANE ASIC flow is placement. The synthesized netlist is to be placed on the floorplan. Placement is perfomed in 2 stages:

    1. Global Placement: It finds optimal position for all cells which may not be legal and cells may overlap. Optimization is done through reduction of half parameter wire length.
    2. Detailed Placement: It alters the position of cells post global placement so as to legalise them.

  • 2. To run the Placement use the command: run_Placement.

  • 3. Post placement: the design can be viewed on magic within results/placement directory. Run the follwing command in that directory:

    magic -T /home/vinay/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.nom.lef def read iiitb_rv32i.def &
    

    

  • 4. sky130_vsdinv cell post placement:

    

  • 5. sky130_vsdinv cell post placement after using expand command in the tkcon window:

  • 6. Area report post placement_resizing:

    

  • 7. sky130_vsdinv slack post placement_resizing_sta:

    

  • 8. Post placement slack report:

    

  • **9.

• 7 . CLOCK TREE SYNTHESIS

  • 1. The purpose of building a clock tree is enable the clock input to reach every element and to ensure a zero clock skew. H-tree is a common methodology followed in CTS. Before attempting a CTS run in TritonCTS tool, if the slack was attempted to be reduced in previous run, the netlist may have gotten modified by cell replacement techniques. Therefore, the verilog file needs to be modified using the write_verilog command. Then, the synthesis, floorplan and placement is run again.

  • 2. To run CTS use the below command:

    run_cts
    

    

  • 3. Slack report post_cts:

    

  • 4. Power report post_cts:

    

  • 5. Clock skew report post_cts:

    

    Performance report:**

    

• 8 . ROUTING

  • 1. OpenLANE uses the TritonRoute tool for routing. There are 2 stages of routing:

    1. Global routing: Routing region is divided into rectangle grids which are represented as course 3D routes (Fastroute tool).
    2. Detailed routing: Finer grids and routing guides used to implement physical wiring (TritonRoute tool).

  • 2. Features of TritonRoute:

    1. Honouring pre-processed route guides
    2. Assumes that each net satisfies inter guide connectivity
    3. Uses MILP based panel routing scheme
    4. Intra-layer parallel and inter-layer sequential routing framework

  • 3. Running routing step in TritonRoute as part of openLANE flow:

    run_routing
    

    

  • 4. Do know in routing stage

    1. run_routing - To start the routing
    2. The options for routing can be set in the config.tcl file.
    3. The optimisations in routing can also be done by specifying the routing strategy to use different version of TritonRoute Engine. There is a trade0ff between the optimised route and the runtime for routing.
    4. The routing stage must have the CURRENT_DEF set to pdn.def.
    5. The two stages of routing are performed by the following engines:
       • Global Route : Fast Route
       • Detailed Route : Triton Route
    6. Fast Route generates the routing guides, whereas Triton Route uses the Global Route and then completes the routing with some strategies and optimisations for finding the best possible path connect the pins.

  • 5. Layout in magic tool post routing: the design can be viewed on magic within results/routing directory. Run the follwing command in that directory:

    magic -T /home/vinay/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.nom.lef def read iiitb_rv32i.def &
    

    

  • 6. sky130_vsdinv cell post routing:

    

  • 7. sky130_vsdinv cell post routing after using expand command in the tkcon window:

    

  • 8. congestion report post routing:

    

  • 9. slack report post routing:

    

  • 10. Area using box command:

    

• Post-synthesis Gate count:-

  

• Area using Box command:-

  

• Slack and performance using report_checks command:-

  

                                1
  Max Performance =  ------------------------
                       clock period - slack
  

• flip-flop to standard cell ratio:-

  

  
        Flip-Flop ratio = Number of D Flip flops 
                          ______________________
                          Total Number of cells
  

• Total power report:-

  

• Vinay Rayapati

• Vinay Rayapati
• Kunal Ghosh

• Kunal Ghosh, Director, VSD Corp. Pvt. Ltd.
• Dr.Murali, Co-ordinator(M.Tech), IIIT Bangalore.
• Dr.Madhav Rao, ECE Department, IIIT Bangalore.

• Jim Ledin “Modern Computer Architecture and Organisation" (2022)

• Vinay Rayapati,Post-Graduate student,International Institute of Information Technology Bangalore,vinayrayapati@outlook.com
• Kunal Ghosh, Director, VSD Corp. Pvt. Ltd.,kunalghosh@gmail.com
• Dr.Murali, Co-ordinator(M.Tech), IIIT Bangalore,coordinator-mtech@iiitb.ac.in
• Dr.Madhav Rao, ECE Department, IIIT Bangalore,mr@iiitb.ac.in