RISC-V based MiniSoC supporting Wave-Pipelined Dynamic-Interleaved-Multi-Threading

It is important to notice, that each wave is an individual thread, so there is no (register-file) dependency between the waves.

System-Hyper-Pipelined MiniSoC

232 MHz running 3 waves

8 independent threads

RV32iMC-P3C4D8W3

Timer with 128 programmable events

32 GPIOs with programmable trigger-units for SW-defined protocols

SkyWater 0,13µm, Efabless Shuttle 8

OpenSource tools: Caravel\OpenLane

Sponsored by Efabless and Google !!!

You can find the FPGA version here (w/o wave-pipelining, but using registers instead): https://github.com/cloudxcc/Arduissimo