❗ Important Note |
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This project simulates the design of a paralle in parallel out shift register using verilog HDL. A parallel in parallel out shift register works in a similar way as a parallel in serial out shift register. The only difference is that the output is taken parallely instead of serially. Thats why the name given as parallel in parallel out shift register.In this design, four D-Flip-flops are used with clock and input signals.