- Implements an universal shift register to perform various operation
- The design is written in verilog using structural model
- With the current implementation the design performs the following operations based on a control input:
- Parallel Load
- Right shift
- Left shift
- Serial-In
| ctl-bit 0 | ctl-bit 1 | OPERATION |
|---|---|---|
| 0 | 0 | LOAD |
| 0 | 1 | RIGHT SHIFT |
| 1 | 0 | LEFT SHIFT |
| 1 | 1 | SERIAL-IN |
sudo apt-get update
sudo apt-get install git
sudo apt-get install yosys
sudo apt-get install docker
git clone https://github.com/subash92-16/universal_shift_register.git
cd universal_shift_register
make setup
make simenv
make verify-all-rtl
make harden
cd universal_shift_register
make clean
make clean-user_project_wrapper
make clean-user_proj_example
Refer to README for a quickstart of how to use caravel_user_project
Refer to README for this sample project documentation.