This project contains a test chip for several OpenRAM memory configurations. The configurations have varying levels of verification. In particular, it has these sizes:

• sky130_sram_1kbyte_1rw1r_8x1024_8 SRAM0
• sky130_sram_1kbyte_1rw1r_32x256_8 SRAM1
• sram_2kbyte_32b_2bank SRAM2 (2 x sky130_sram_1kbyte_1rw1r_32x256_8)
• sky130_sram_2kbyte_1rw1r_32x512_8 SRAM3
• sky130_sram_4kbyte_1rw1r_32x1024_8 SRAM4
• sky130_sram_2kbyte_1rw1r_32x512_8 SRAM5
• sky130_sram_4kbyte_1rw1r_32x1024_8 SRAM6
• sky130_sram_1kbyte_1rw_32x256_8 SRAM8
• sky130_sram_2kbyte_1rw_32x512_8 SRAM9
• sky130_sram_2kbyte_1rw_32x512_8 SRAM10

There are three test modes available. Each one inputs a packet that configures the read and write operations of a particular SRAM. The io_in[1] and io_in[0] determines the clock the design runs on.

{io_in[1], io_in[0]}
2'b00 : clock is provided through LA (la test mode)
2'b01 : clock is provided through io_in[11] (gpio test mode)
2'b10 : clock is provided through wb_clk_i (wishbone test mode)

The test packet is a 112-bit value that has the follow signals and bit size:

• chip_select (4)
• addr0 (16)
• din0 (32)
• csb0 (1)
• web0 (1)
• wmask0 (1)
• addr1 (16)
• din1 (32)
• csb1 (1)
• web1 (1)
• wmask1 (4)

During a read operation, the din bits are replaced with the data output bits so that they can be verified.

Note: The 64-bit memory leaves the middle 32-bits as a value of 0 and instead reads/writes the upper and lower 16-bits to reduce the number of packet bits.

In GPIO mode, the test packet is scanned in/out with the GPIO pins in 112 cycles. The GPIO pins used are as follows:

• Mode select: io_in[1:0] = 2'b01
• Scan reset: io_in[2]
• Scan clock: io_in[3]
• Scan enable: io_in[4]
• Load SRAM result into register: io_in[5]
• CSB for all SRAM: io_in[6]
• Scan input: io_in[7]
• Scan output: io_out[8]

In LA mode, the test packet is directly written from the output of the 128-bit LA.

• Mode select: io_in[1:0] = 2'b00
• Control register clock: la_data_in[127]
• Load control register: la_data_in[125]
• Load SRAM result into register: la_data_in[124]
• CSB for all SRAM: la_data_in[123]

The wishbone mode tests the memories through the wishbone interface. The interface is used to provide data packet to the memories based on the address map of each memory.

• Mode select: io_in[1:0] = 2'b10
• CSB for all SRAM: wbs_cyc_i, wbs_stb_i and wbs_adr_i
• Data for all SRAM: wbs_dat_i
• Write enable for all SRAM: wbs_we_i

Muhammad Hadir Khan mkhan33@ucsc.edu Jesse Cirimeli-Low jcirimel@ucsc.edu Amogh Lonkar alonkar@ucsc.edu Bugra Onal bonal@ucsc.edu Samuel Crow sacrow@ucsc.edu Matthew Guthaus mrg@ucsc.edu