Accumulator based 2D parallel architecture (N-outputs at a time), area and throughput efficient IDCT/IDST architecutre for hevc standard
Open Source Digital ASIC Design requires three open-source components:
- RTL Designs = github.com, librecores.org, opencores.org
- EDA Tools = OpenROAD, OpenLANE,QFlow
- PDK = Google + Skywater 130nm Production PDK
Design has been carried out using Skywater 130nm PDK using openLANE and caravel open source silicon development tools,
DWT - Conventional 5/3 lifting based wavelet with 3 octaves.
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Refer to README for a quickstart of how to use caravel_user_project
Refer to README for this sample project documentation.