DRC: Passing

LVS: Passing

Parasitic extraction: Done

PEX Simulation: Done

Circuit Description/Design Goals

Simulated Performance Summary

Block Diagram

Schematics

Layout

Simulations

Final Steps

Our design is a novel high-gain, high-speed, low-noise transimpedance amplifier based on a resistive feedback op amp design. Our design leverages differential sensing of the photodiode, allowing for a truly differential circuit design without duplicating the optical signals. Our goals are to have a low enough noise floor to enable persistence of quantum data while amplifying signals to measurable levels (high-gain). With these goals being met, the intent is to maximize amplifier speed. This top-level TIA design and the core op-amp will be very valuable to the open-source community. However, this circuit has been designed for integration with photonic ICs to enable QRNG.

Quantum Random Number Generation (QRNG) uses the inherent randomness of quantum mechanics to produce random numbers which are information-theoretically provable, truly random (as opposed to pseudorandom), and pass existing standard benchmarks. On-chip QRNG has been done before; however, what makes this project unique is that we use a 90° optical hybrid and have moved the detector circuit (TIA) from an external PCB to silicon, improving performance of the system. Both advances will allow for future research beyond QRNG into other useful quantum information such as quantum state tomography, quantum key distribution (QKD), and more.

Table 1 – Simulated Performance Summary.

Simulated performance is satisfactory for purposes as electronic amplifier for quantum information to be preserved.

Figure 1 – Diagram of test setup.

Figure 2 – Top level schematic.

Figure 3 – Top level schematic in Xschem (flattened) - click for detail.

Figure 4 – Schematic of core amplifier (x2).

Figure 5 – Common-mode feedback amplifier schematic (x2).

Figure 6 – Schematic of current mirror (x3 with variations).

Figure 7 – Schematic of output buffer.

Figure 8 – Basic floorplan.

Figure 9 – Top level layout.

Figure 10 – Layout of core amplifier (x2).

Figure 11 – Common-mode feedback amplifier layout (x2).

Figure 12 – Layout of current mirror (x3 with variations).

Figure 13 – Layout of output buffer.

Figure 14 – Layout of compensation capacitor.

Figure 15 – Plot of transimpedance gain.

Figure 16 – Gain and phase plot of core amplifier loop.

Figure 17 – Gain and phase plot of cmfb amplifier loop (x2).

Improve symmetry of core amplifier layout.

Run parasitic simulation.

Caravan integration.