The purpose of this project is to produce clean GDS (Graphic Design System) Final Layout with all details that is used to print photomasks used in fabrication of a behavioral RTL (Register-Transfer Level) of a 10-bit Serializer, using SkyWater 130 nm PDK (Process Design Kit)

1. About The Project
2. Pin Configuration
3. Functional Diagram and Description
4. RTL to GDSII Introduction
5. Pre-Layout
   • Simulation
6. OpenLane
   • Installation
   • Running OpenLane
7. Synthesis
8. Floorplanning
9. Placement
10. Routing
11. Final Layout
12. Post-layout
    • Simulation
13. Summary
14. Area of improvement
15. References
16. Acknowledgement
17. Author

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault, OpenPhySyn, SPEF-Extractor and custom methodology scripts for design exploration and optimization. It is a tool started for true open source tape-out experience and comes with APACHE version 2.0. The goal of OpenLANE is to produce clean GDSII without any human intervention. OpenLANE is tuned for Skywater 130nm open-source PDK and can be used to produce hard macros and chips.

From conception to product, the ASIC design flow is an iterative process that is not static for every design. The details of the flow may change depending on ECO’s, IP requirements, DFT insertion, and SDC constraints, however the base concepts still remain. The flow can be broken down into 11 steps:

1. Architectural Design – A system engineer will provide the VLSI engineer with specifications for the system that are determined through physical constraints. The VLSI engineer will be required to design a circuit that meets these constraints at a microarchitecture modeling level.

2. RTL Design/Behavioral Modeling – RTL design and behavioral modeling are performed with a hardware description language (HDL). EDA tools will use the HDL to perform mapping of higher-level components to the transistor level needed for physical implementation. HDL modeling is normally performed using either Verilog or VHDL. One of two design methods may be employed while creating the HDL of a microarchitecture:

   a. RTL Design – Stands for Register Transfer Level. It provides an abstraction of the digital circuit using:

   • i. Combinational logic
   • ii. Registers
   • iii. Modules (IP’s or Soft Macros)

   b. Behavioral Modeling – Allows the microarchitecture modeling to be performed with behavior-based modeling in HDL. This method bridges the gap between C and HDL allowing HDL design to be performed

3. RTL Verification - Behavioral verification of design

4. DFT Insertion - Design-for-Test Circuit Insertion

5. Logic Synthesis – Logic synthesis uses the RTL netlist to perform HDL technology mapping. The synthesis process is normally performed in two major steps:

   • GTECH Mapping – Consists of mapping the HDL netlist to generic gates what are used to perform logical optimization based on AIGERs and other topologies created from the generic mapped netlist.

   • Technology Mapping – Consists of mapping the post-optimized GTECH netlist to standard cells described in the PDK

6. Standard Cells – Standard cells are fixed height and a multiple of unit size width. This width is an integer multiple of the SITE size or the PR boundary. Each standard cell comes with SPICE, HDL, liberty, layout (detailed and abstract) files used by different tools at different stages in the RTL2GDS flow.

7. Post-Synthesis STA Analysis: Performs setup analysis on different path groups.

8. Floorplanning – Goal is to plan the silicon area and create a robust power distribution network (PDN) to power each of the individual components of the synthesized netlist. In addition, macro placement and blockages must be defined before placement occurs to ensure a legalized GDS file. In power planning we create the ring which is connected to the pads which brings power around the edges of the chip. We also include power straps to bring power to the middle of the chip using higher metal layers which reduces IR drop and electro-migration problem.

9. Placement – Place the standard cells on the floorplane rows, aligned with sites defined in the technology lef file. Placement is done in two steps: Global and Detailed. In Global placement tries to find optimal position for all cells but they may be overlapping and not aligned to rows, detailed placement takes the global placement and legalizes all of the placements trying to adhere to what the global placement wants.

10. CTS – Clock tree synteshsis is used to create the clock distribution network that is used to deliver the clock to all sequential elements. The main goal is to create a network with minimal skew across the chip. H-trees are a common network topology that is used to achieve this goal.

11. Routing – Implements the interconnect system between standard cells using the remaining available metal layers after CTS and PDN generation. The routing is performed on routing grids to ensure minimal DRC errors.

The Skywater 130nm PDK uses 6 metal layers to perform CTS, PDN generation, and interconnect routing. Shown below is an example of a base RTL to GDS flow in ASIC design:

Commands to use :

Obtained GTKWave :

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

For more details : here

1. Synthesis
   • yosys - Performs RTL synthesis
   • abc - Performs technology mapping
   • OpenSTA - Performs static timing analysis on the resulting netlist to generate timing reports
2. Floorplan and PDN
   • init_fp - Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing)
   • ioplacer - Places the macro input and output ports
   • pdn - Generates the power distribution network
   • tapcell - Inserts welltap and decap cells in the floorplan
3. Placement
   • RePLace - Performs global placement
   • Resizer - Performs optional optimizations on the design
   • OpenDP - Perfroms detailed placement to legalize the globally placed components
4. CTS
   • TritonCTS - Synthesizes the clock distribution network (the clock tree)
5. Routing
   • FastRoute - Performs global routing to generate a guide file for the detailed router
   • CU-GR - Another option for performing global routing.
   • TritonRoute - Performs detailed routing
   • SPEF-Extractor - Performs SPEF extraction
6. GDSII Generation
   • Magic - Streams out the final GDSII layout file from the routed def
   • Klayout - Streams out the final GDSII layout file from the routed def as a back-up
7. Checks
   • Magic - Performs DRC Checks & Antenna Checks
   • Klayout - Performs DRC Checks
   • Netgen - Performs LVS Checks
   • CVC - Performs Circuit Validity Checks

• Preferred Ubuntu OS)
• Docker 19.03.12+
• GNU Make
• Python 3.6+ with PIP
• Click, Pyyaml: pip3 install pyyaml click

git clone https://github.com/The-OpenROAD-Project/OpenLane.git
cd OpenLane/
make openlane
make pdk
make test # This a ~5 minute test that verifies that the flow and the pdk were properly installed

For detailed installation process, check here

make mount

• Note
  • Default PDK_ROOT is $(pwd)/pdks. If you have installed the PDK at a different location, run the following before make mount:
  • Default IMAGE_NAME is efabless/openlane:current. If you want to use a different version, run the following before make mount:

The following is roughly what happens under the hood when you run make mount + the required exports:

export PDK_ROOT=<absolute path to where skywater-pdk and open_pdks will reside>
export IMAGE_NAME=<docker image name>
docker run -it -v $(pwd):/openLANE_flow -v $PDK_ROOT:$PDK_ROOT -e PDK_ROOT=$PDK_ROOT -u $(id -u $USER):$(id -g $USER) $IMAGE_NAME

For verification :

Command : run_synthesis

Successful :

Command used :

Yosys synthesis :

# User config
set ::env(DESIGN_NAME) vsdserializer_v1

# Change if needed
set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]

# Fill this
set ::env(CLOCK_PERIOD) 10
set ::env(CLOCK_PORT) "clk"

set ::env(FP_CORE_UTIL) 25
set ::env(PL_TARGET_DENSITY) 1

set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
if { [file exists $filename] == 1} {
	source $filename
}

Command used : run_floorplan

For invoking :

Floorplanning viewed :

Command : run_placement

Placement analysis :

Placement routing resources :

Final Congestion report :

And then run the following command :

To obtain :

Command used : run_routing

Routing resources analysis :

Final Congestion report :

Completed detail routing :

Routing successful :

Commands are used in the following path as shown in the figure :

Files available in Magic folder is as shown :

• Layout after floorplanning and placement in Magic :

Command used : magic vsdserializer_v1.mag

Close view :

• Final GDS Layout :

Command used : magic vsdserializer_v1.gds

Closer look :

• lef Layout :

Command used : magic vsdserializer_v1.lef.mag

• tkcon window :

Commands used :

GTKWave obtained :

Clone it using the command : git clone https://github.com/Devipriya1921/vsdserializer_v1.git

• Complete details can be found in the design folder :

vsdserializer_v1
├── config.tcl
├── runs
│   ├── first_run
│   │   ├── config.tcl
│   │   ├── logs
│   │   │   ├── cts
│   │   │   ├── cvc
│   │   │   ├── floorplan
│   │   │   ├── klayout
│   │   │   ├── magic
│   │   │   ├── placement
│   │   │   ├── routing
│   │   │   └── synthesis
│   │   ├── reports
│   │   │   ├── cts
│   │   │   ├── cvc
│   │   │   ├── floorplan
│   │   │   ├── klayout
│   │   │   ├── magic
│   │   │   ├── placement
│   │   │   ├── routing
│   │   │   └── synthesis
│   │   ├── results
│   │   │   ├── cts
│   │   │   ├── cvc
│   │   │   ├── floorplan
│   │   │   ├── klayout
│   │   │   ├── magic
│   │   │   ├── placement
│   │   │   ├── routing
│   │   │   └── synthesis
│   │   └── tmp
│   │       ├── cts
│   │       ├── cvc
│   │       ├── floorplan
│   │       ├── klayout
│   │       ├── magic
│   │       ├── placement
│   │       ├── routing
│   │       └── synthesis
├── src
|   ├── vsdserializer_v1.v
├── pre_layout
|   ├── vsdserializer_v1
|   ├── vsdserializer_v1.v
|   ├── vsdserializer_v1.v.vcd
|   ├── vsdserializer_v1_tb.v
|   ├── vsdserializer_v1_tb.vcd
├── post_layout
|   ├── gls
|   ├── gls.v
|   ├── primitives.v
|   ├── sky130_fd_sc_hd.v
|   ├── vsdserializer_v1.synthesis.v
|   ├── vsdserializer_v1_vcd
|   ├── vsdserializer_v1_tb.vcd

   

• Improvement in the design and integration of Power pins.
• To perform spice simulation of the final GDS layout.

• GitLab/OpenLane workshop
• The OpenROAD Project/OpenLane
• https://youtu.be/d0hPdkYg5QI

• Kunal Ghosh, Founder, VSD Corp. Pvt. Ltd

• A Devipriya, Bachelor of Engineering in Electronics and Communication Engineering, Bangalore