Table of Contents
The block diagaram of the PLL as a clock multiplier is as follows:
Here M = 8
Tested through spice simulations on skywater 130nm ss corner at room termperature
| Parameter | Description | min | typ | max | Unit | Conditions |
|---|---|---|---|---|---|---|
| VDD | Digital Supply | - | 1.8 | - | V | T = 27C |
| FCLKREF | Reference | 5 | - | 12.5 | MHz | T = 27C |
| FCLKOUT | Output Clock | 40 | - | 100 | MHz | PLL Mode, T = 27C |
| FCLKOUT | Output Clock | - | - | - | MHz | VCO Mode, T = 27C |
| JRMS | Jitter (rms) | - | - | - | ps | PLL_Mode |
| DC | Duty Cycle | - | - | - | % | T = 27C |
| TSET | Settling Time | ~37 | - | ~22 | us | T = 27C |
| CL | Load Capacitance | - | - | - | fF | T = 27C |
| IDD | Supply Current | - | - | - | fF | T = 27C |
Red: Clock 2
Blue: Clock 1
Orange: Up Signal
Green: Down Signal
Red: Output Clock
Blue: Input Clock
Red: Charge Pump Output Voltage
The PLL output from the prelayout simulation is as follows:
Red: Reference Clock
Blue: Output Clock Divided by 8
Yellow: Down Signal
Brown: Up Signal
Pink (at top): ChargePump output
- Clone this repo.
- cd <repo_name>/Prelayout
- open the PLL_PreLay.cir and change .include /home/Characterization-TCL-flow-for-8x-PLL-Clock-Multiplier-for-sky130-Process-Corners/sky130nm.lib accordingly .
- Run the PLL circuit by typing
ngspice PLL_PreLay.cir
Subham Mohapatra - subham.m08@gmail.com