Soric is an open heterogeneous SoC targeting for application in cryptography and trusted devices. The SoC consists of two RISC-V cores, 4x2kB SRAM and Peripherals (e.g., UART, GPIO). One of the cores supports the RISC-V scalar cryptography extension V1.0.0 [1] which is specified for cryptographic and security critical applications while the other core is responsible for the security non-critical applications.
├── bin - scripts (e.g., environment configuration)
├── caravel - contains the clone of the frontend management system for efabless user projects.
├── doc - consists of documents.
├── gds - Compressed gds file of the Soric layout.
├── openlane - Scripts for implementing the macros and Soric using OpenLane tools.
├── verilog - HDL codes and verifications
│ ├── dv - the verification of integrating Soric into the Caravel system at RTL and Gate Level netlist
│ ├── gl - Generated gate level netlists of Soric for verification
│ └── rtl - verilog codes of Soric
└── others(def, lef,...) - contains other outputs to adhere to the same directory structure of the efabless caravel user project.
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For seting up the repository
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Clone the repository and setup environment
git clone https://github.com/phthinh/soric_project.git ./soric_project cd ./soric_project -
Fix paths of the env. variables in bin/conf.sh file suitable for your machine, and
source bin/conf.sh
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Refer to README for the efabless caravel user project documentation to:
- Install and integrate the caravel system
- Build the Sky130 PDK
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Run tests on Soric. Notes that Soric includes two cores of which functions are verified with more comprehensive tests on other repos. For example, the ibex core and crypto core are tested in lowrisc ibex [2], and crypto ibex [3]. Here are the tests for the integration of Soric into the caravel user project.
- To test memory access from the caravel systems to the Soric's srams
at RTL level
make -C verilog/dv/soric_mem_test
at gate level
make -C verilog/dv/soric_mem_test SIM=GL
- To test downloading and running a simple program on Soric from the caravel system
at RTL level
make -C verilog/dv/soric_simple_test
at gate level
make -C verilog/dv/soric_simple_test SIM=GL
- To test downloading and running a program testing some crypto instructions.
at RTL level
make -C verilog/dv/soric_crypto_test
at gate level
make -C verilog/dv/soric_crypto_test SIM=GL
[1] RISC-V Scalar Cryptography Extension Specification, https://github.com/riscv/riscv-crypto/releases/tag/v1.0.0-rc6-scalar/riscv-crypto-spec-scalar-1.0.0-rc6.pdf