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DDR3 SSTL Test
public project
MPW-5   

This design will allow for very basic testing of our DDR3 SSTL circuit (the DUT).

The SSTL is a necessary part of DDR3 memory controller. It is the driver circuit for the data lines, and also serves as the termination when the controller is receiving data.

In the future, we hope to incorporate the DUT into a fully open source DDR3 controller for the sky130 (or future skywater) processes.

project layout image
project layout image
Layout Image
Owner
derekcom17
Organization URL

https://www.bsg.ai/

Description

Test chip for a DDR3 SSTL driver. This chip will evaluate the performance of this this circuit, and test emulation of the DDR3 calibration process.

Version

0.1

Category

gpio

Process

sky130A