graph TD
A(A SoC Wish List) -- SoC Description in Chisel--> B
B[The Rocket SoC Generator] --SoC RTL--> D[The OpenLane Flow]
C[Caravel SoC Harness] --Harness RTL--> D
B --FPGA RTL--> L
P[RISC-V IDE Tools]--Code and Executables-->H
L[_Yosys_+nextpnr] --Bitstream--> K[Lattice ECP5 Eval Board]
E(Caravel Firmware)  --Init, Monitoring, Debug--> C
D --Sky130 GDS II Layout Data--> F[eFabless MPW]
O[Xschema]--Circuit schematics-->J
F --MPW Chips--> H
F --MPW Chips--> I
I[Caravel EVB] --Breadboarding-->H{User system}
J[KiCad]--Gerber and BOM-->H

sequenceDiagram
Note right of System: Powers<br/>Caravel<br/>Chip.
System -->> Harness: Reset
System -->> Harness: Reset
System -->> Caravel SoC: Reset
Harness -->> Caravel SoC: core clock
Harness -->> Caravel SoC: core reset
Caravel SoC->>Harness: Configuration of clk, DLL
Caravel SoC->>Harness: Configure pad data routing and GPIO
Harness-->>Rocket SoC: Set user_clock full speed
Caravel SoC->>Rocket SoC: Reset user logic
Note left of Rocket SoC: Rocket boots<br/>from ROM logic<br/>XIP SPI flash<br/>runs on DTIM.
Rocket SoC -->> Caravel SoC: Rocket is running OK
Note left of Caravel SoC: Acknoleging <br/>Rocket OK<br/>tuns off External<br/>CPG power<br/>via GPIO or I2C.
Caravel SoC->>System: Turn off External CPG Power
Note left of Rocket SoC: Rocket sends message<br/>"Bring Caravel<br/>to lowest power state"<br/>e.g. wishbone mailbox<br/>and interrupt.
Rocket SoC->>Caravel SoC: "Go low on power"
Note left of Caravel SoC: Management SoC sets<br/>Clocking and DLL<br/> to Caravel's<br/>lowest power state<br/>via System control.
Caravel SoC->> Harness: Caravel goes low power.
Note left of Rocket SoC: Rocket gets<br/>wake up signal<br/>from RTC.
Rocket SoC->>Caravel SoC: "Go full power"
Caravel SoC->>Harness: Configure Clock, DLL via System control
Caravel SoC->>Rocket SoC: "Went full power".