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DC-DC Buck...
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Three-Level Flying Capacitor DC-DC Buck Converter for High-Efficiency Energy Power Sources in CubeSat Applications

I.- Motivation

Recent developments in satellite technology miniaturization have led to the widespread use of the CubeSat standard, based around a form factor consisting of 10 cm cubes. Due to the demanding volume and weight limitations inherent to aerospace applications, and especially under the miniaturized satellite paradigm,  electronic power systems (EPS) are an essential subsystem and a good target for optimization since batteries and power circuits tend to be bulky and heavy. Fully integrated DC-DC converters are therefore an essential building block in future EPS architectures, because of their elimination of bulky and expensive off-chip inductors and capacitors and their great reduction of PCB footprints. The three main functions of DC-DC converters in the context of CubeSat EPS structures appear in Fig. 1, from left to right, as described below:

  1. Photovoltaic (PV) cells to DC bus: The three photo-voltaic input channels (one channel per pair of CubeSat sides) need to be converted from high voltages (in the case of several PV cells connected in series, e.g. 3U CubeSats) to lower non-regulated voltages applied to the DC bus. Depending on the technology, the connection type and the radiation conditions, the nominal voltage provided by the PV cells is around 20V. On the DC bus side, the nominal voltage is set to 12V [1]. 
  2. DC bus to batteries: The DC bus non-regulated voltage is processed by a second DC-DC converter stage to provide power for battery recharge. The battery has a nominal value of 8V, as in the example in [1].
  3. Batteries to TTL/CMOS domains: Finally, a third stage of DC-DC converters provides regulated voltages for TTL (5V) and CMOS (3.3V) voltage levels, which source the CubeSat functional subsystems and payloads.

Based on a literature review, we propose the idea of tackling the PV-cell-to-DC-bus DC-DC conversion problem using fully-integrated interleaved switched-capacitance modules, which allow an efficient and highly compact solution to be used as the main building block for CubeSat EPS.

Figure 1: Typical CubeSat EPS architecture, as in [1]

II.- Description

In recent years, flying capacitor multi-level (FCML) converters have demonstrated promising performance when used as building blocks for fully integrated conversion systems such as interleaved DC-DC converters [3], [4] and hybrid switched-capacitor DC-DC converters [5], [6]. In the context of space applications, power conversion efficiency is of the utmost importance, since batteries cannot be recharged externally and solar panel power is limited by the reduced area available on the 6 faces of standard CubeSats and the solar radiation time. 

Our project focuses on designing and implementing a DC-DC buck converter demonstrator based on the three-level flying capacitor converter (3L-FCC) architecture, a simple but versatile type of FCML converter, using the Skywater 130nm CMOS technology (SKY130). Since power conversion at low voltage levels has already been demonstrated in the SKY130 technology in previous work [7], we set our focus on the buck conversion block between the high voltages in solar panels (20V) and the intermediate unregulated voltages in the DC bus (12V) for photo-voltaic input channel in CubeSat applications. In our proposed architecture and topologies, depicted in Fig. 2, the power circuits are fully integrated on-chip, including the power MOSFETs (PM), the flying capacitor (FC) and the gate drivers (GD). The switching control will be delivered externally or using the integrated RISC-V module, to allow for experiments with different modulation and control schemes. 

Since traditional step-down topologies are limited by the size and performance of passive components, particularly inductors [5], the output filter inductor of our testchip will be switchable between an on-chip passive and an off-chip discrete component, for characterization purposes. The project is conceived so that the core conversion module can be copied N times. Initially, N = 2, but it could be higher depending on the core circuit area, improving the conversion efficiency. It is worth noting that we focus on the step-down conversion application, but the topology allows for bidirectional conversion in case it is needed for a step-up application. Furthermore, the integration level can be increased in future versions of the silicon demonstrator, including e.g. digital PID feedback, thermal management control, photovoltaic maximum-power-point-tracking (MPPT) algorithms and battery management systems (BMS). Therefore, this first version tackles the feasibility issues related to power circuits (i.e. high voltages and high currents) using the SKY130 technology.


Figure 2:  Block diagram of the full DC-DC system and schematic of the core circuit to be implemented, based on the core structure in [3].

Table 1: Electrical Specifications for a single-core 3LFCC.

Table notes:

  1. In [7], a current of 300mA has been verified in measurements, and thus we consider it as a realistic starting point.

  2.  The Caravel GPIO allows up to 60MHz signal frequencies, limiting the clock speed provided from off-chip sources. We are also investigating the possibility of using the DLL clock in the Caravel to generate the triggering signals at higher frequencies.

  3.  Based on the EPS specification in [2], but subject to change after a more detailed study.

III.- Design Goals

The goal of this project is to design a DC-DC power converter testchip for CubeSat applications focusing on the high-voltage PV-cell-to-DC-bus stage, but extendable to other conversion stages in the context of CubeSat EPS based on our modular design approach and the wide conversion rate inherent to FCML converters [8]. The reconfigurable approach will allow the study of different configurations regarding number of cores and passive values, focusing on the electrical specifications described in Table 1, set as reasonable values for the intended application. Our work aims to maximize the output power rating based on a combination of switching control schemes and interleaving operation, to achieve 300mA-level currents as the ones presented in previous work [7] or higher.

The specific goals of our project are:

  1. Design and simulation of an open source DC-DC  converter core circuit in the SKY130 technology, which can be used as a building block for future hybrid power electronic projects.
  2. Optimization of the circuit realization in the SKY130 technology, mainly based on passive (C and L) component floorplan minimization using design parameters such as switching frequency, number of interleaving cores and optimal control schemes, to name the most relevant.
  3. The use of knowledge generated within the open source IC design community to solve our own design challenges, mostly concerning power device implementation and on-chip inductor element layout.
  4. Chip measurement and validation in cooperation with Universidad Nacional del Sur (Argentina), leveraging an inter-university regional network for specific topics in integrated circuit design using open source EDA.

IV.- Methodology

Our methodology workflow is depicted in Fig. 3. The iterative workflow allows a progressive integration of the different parts of the project. The different components, such as power switched-capacitor circuit, drivers, filter, control and testing capabilities, can be designed and simulated individually before assembling the entire architecture. Splitting the project in generic building blocks enables the use of available designs, such as [7], giving a more simple work approach. On the other hand, it could increase our contributions to the open source community, as both the core converter module and the different sub-modules could be reused in multiple types of hybrid systems. Moreover, regarding the task and workload management, this allows to assign tasks according to the different backgrounds of the members and encourage the participation of the members with lesser experience in IC design.

Figure 3:  Design and testing methodology of the project

V.- Preliminary study

To have a first idea of the feasibility of our project, we studied the main limiting factors for its realization. The two main challenges that we identified are:

  1. The available chip area and the capabilities of the SKY130 technology are compatible with the project requirements.
  2. The device, passive and metallization parasitics and nonidealities allow to achieve the target efficiency.

Regarding challenge 1, the first part of our investigation was related to voltage and current rating. The SKY130 technology includes high voltage devices VDS_MAX up to 22V and VGS_MAX up to 5V, which allows it to handle the voltages required in CubeSat EPS applications. 

Secondly, we studied the proposal and results available in [7], to confirm that currents up to 300mA can be managed on chip in SKY130 according to silicon measurements. Part of our efforts are currently focused on finding out how much this limit can be increased based on the bonding pad and metallization current driving capabilities in SKY130. 

Lastly, we worked on the relationship between the chip area and the different design variables involved. We mainly focused on passive component sizing, since they constitute the bulk of the needed area in such applications. We used the PDK information to run a simple circuit-level simulation of the schematic in Fig. 4, which includes the power transistors, the flying capacitor, the output filter and a load. The passive components, the signal source and the drivers are modeled as ideal components. The device sizing is inherited from the project in [7], which uses ~300mA current levels. In Fig. 5, the simulated input and output waveforms are shown. The top plot in Fig. 5 shows the basic open-loop triggering scheme, in which the pairs of switches are activated sequentially spaced by a dead time, with the same period length in all the cycles (D1 ON/D2OFF, D1 OFF/D2 OFF, D1 OFF/ D2 ON). The middle plot in Fig. 5 shows the output voltages before and after the LC filter, VOUT_CORE and VOUT, respectively. The third panel in Fig. 5 shows the current flowing in the load, I_VS_RL. In Table 2, the main parameters used in the simulation are summarized. From the simulation results, we can conclude that reasonable current and voltage output DC and ripple values can be achieved for the nominal input voltage and switching frequency. Given the density of MIM capacitors provided in the SKY130 documentation, the capacitor values are manufacturable in the given user area of the Caravel chip. In the case of the inductor, we don’t have verified estimations of the area needed, but previous projects in SKY130 [9] suggest that a 5nH inductor fits in the user area of the Caravel chip. Therefore, the combination of the parameters used for simulation are a realistic starting point to iterate towards an optimized solution.

Figure 4:  Schematic view of the spice simulation used to validate passive component sizing.

Figure 5:  Plot of the relevant input and output waveforms for the preliminary simulation.

Table 2: Relevant circuit simulation parameters used in the preliminary study.

Regarding challenge 2, the nonideal effects in active devices, passive elements and metallization which can produce parasitic effects or switching leakage have not been analyzed at this stage, and therefore are part of our current efforts.

VI.- References

[1] Y. Murga, C. A. Rojas, S. Kouro and N. Muller, "Modelling of Non-Isolated Photovoltaic Energy Power Source for 3U NanoSats," 2021 IEEE International Conference on Automation/XXIV Congress of the Chilean Association of Automatic Control (ICA-ACCA), 2021, pp. 1-6, doi: 10.1109/ICAACCA51523.2021.9465291.

[2] GOMSpace Electrical Power Supply system for small nanosatellites NanoPower P31u Datasheet, https://gomspace.com/UserFiles/Subsystems/datasheet/gs-ds-nanopower-p31u-30.pdf

[3] Choi, M.; Jeong, D.-K. Design of Soft-Switching Hybrid DC-DC Converter with 2-Phase Switched Capacitor and 0.8nH Inductor for Standard CMOS Process. Electronics 2020, 9, 372. https://doi.org/10.3390/electronics9020372 

[4] Lee, J.-Y.; Kim, G.-S.; Oh, K.-I.; Baek, D. Fully Integrated Low-Ripple Switched-Capacitor DC–DC Converter with Parallel Low-Dropout Regulator. Electronics 2019, 8, 98. https://doi.org/10.3390/electronics8010098

[5] Z. Xia and J. T. Stauth, "A Cascaded Hybrid Switched-Capacitor DC-DC Converter Capable of Fast Self Startup for USB Power Delivery," in IEEE Journal of Solid-State Circuits, doi: 10.1109/JSSC.2022.3162166.

[6] C. Huang and P. K. T. Mok, "A 100 MHz 82.4% Efficiency Package-Bondwire Based Four-Phase Fully-Integrated Buck Converter With Flying Capacitor for Area Reduction," in IEEE Journal of Solid-State Circuits, vol. 48, no. 12, pp. 2977-2988, Dec. 2013, doi: 10.1109/JSSC.2013.2286545.

[7] Open PMIC project @Efabless platform: https://github.com/westonb/Open-PMIC-tapeout

[8] K. Kesarwani and J. T. Stauth, "Resonant and multi-mode operation of flying capacitor multi-level DC-DC converters," 2015 IEEE 16th Workshop on Control and Modeling for Power Electronics (COMPEL), 2015, pp. 1-8, doi: 10.1109/COMPEL.2015.7236511.

[9]  Amsat TXRX IC MPW2 project @Efabless platform: https://github.com/yrrapt/amsat_txrx_ic

VII.- Team Members

  • Christian Rojas: Professor Advisor (1,2)
  • Alejandro Oliva: Professor Advisor (3)
  • Jorge Marin: Team Coordinator, Postdoctoral Fellow (2)
  • Sebastián Neira González: Member, Undergraduate Student (1,2)
  • Alfonso Cortés Neira: Member, Master Student (1,2)
  • Kevin Pizarro Aguirre: Member, Undergraduate Student (1)
  • Vicente Andrade Ercilla: Member, Undergraduate Student (1)
  • Diego Almonacid Villalobos: Member, Undergraduate Student (1)
  • Vicente Osorio Rivas: Member, Undergraduate Student (1)
  • Max Vega Campos: Member, Undergraduate Student (1)
  • Aquiles Viza: Member, Undergraduate Student (1)
  • Carolina Beckmann: Member, Master student (1,2)
  • Tomás Velásquez: Member, Undergraduate Student (1)
  • Pablo Vera: Member, Undergraduate Student (1)
  • Niria Osterman: Member, Team Advisor (4)
  • Alfredo Falcón: Member, Team Advisor (4)
  • Esteban Lindstrom: Member, Team Advisor (4)

(1) Dept of Electronics, Universidad Técnica Federico Santa Maria, Chile

(2) Centro Avanzado de Ingeniería Eléctrica y Electrónica (AC3E), Universidad Técnica Federico Santa María, Chile

(3) Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages" (IIIE), Departamento de Ingeniería Eléctrica y de Computadoras, Universidad Nacional del Sur -CONICET, Argentina

(4) Departamento de diseño de circuitos integrados y sistemas reconfigurables, Instituto Nacional de Tecnología Industrial, Argentina

 

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Owner
JorgeMarinN
Summary

This project aims to design and implement a DC-DC buck converter based on the Three-level Flying Capacitor Converter (3L-FCC) architecture for space applications, namely CubeSat systems, using the Skywater 130nm CMOS technology. In our proposal, the power circuits are fully integrated on-chip, including the power MOSFETs (PM), the flying capacitor (FC) and the gate drivers (GD), to obtain an efficient and compact implementation and contribute with a versatile power electronics building block to the open source IC design community.

Category

power