pll2022

Implementation of a Sub-Sampling PLL targeting SerDes Applications

Submission(s) for precheck - 31.08.2022:

folder "PICO Contest" includes Pin List as well as "pin dummy"(dummy project but with all the correct pins)

Name		Name	Last commit message	Last commit date
Latest commit History 26 Commits
LVS		LVS
PICO Contest		PICO Contest
Verilog		Verilog
gds		gds
mag		mag
spice		spice
xschem		xschem
README.md		README.md
chip_pinout.jpg		chip_pinout.jpg
delaycell_layout.JPG		delaycell_layout.JPG
delaycell_schematic.jpg		delaycell_schematic.jpg
fll_block.jpg		fll_block.jpg
fll_flow.jpg		fll_flow.jpg
gds.JPG		gds.JPG
gds_zoom_label.png		gds_zoom_label.png
hierarchy.jpg		hierarchy.jpg
proposal.jpg		proposal.jpg
vcocore_layout1.JPG		vcocore_layout1.JPG
vcocore_schem1.JPG		vcocore_schem1.JPG
wrapper_gds.png		wrapper_gds.png

ChrisG1997/pll2022