This work presents a Third order SC Cheybshev LPF in a single and short circuit for vital sign processing circuit. The vital sign processing circuit simulates dc elimination and out-of-band interference rejection. This filter (LPF) is used to reduce noise in the circuit. The proposed circuits possess high efficiency in terms of power and current consumption, which is due to the increased area requirement of the chip and noise caused by the use of the OTA in Chebyshev filter design. Moreover, the scheme for generating current output signals using amplifier meets this requirement. However, the noise of the amplifier contributes to the output. Based on the studies, A novel Third order SC Chebyshev LPF implemented in a simple circuit with LNTA. The leap-frog configuration of the LPF is employed to maximize stability and minimize PVT variations.
To investigate the performance of the proposed design, Cadence Virtuoso simulations are used. The simulation results, based on the 45-nm CMOS process technology model, indicate that the proposed design have superior speed and power against other existing design. The proposed design is intended to minimize SNR as well as power consumption. Therefore, a useful metric used in these cases is the power delay product (PDP) which can be used to characterize the overall performance of a system. The PDP can be improved at different levels at the device level, layout level, circuit level, architecture level. The proposed design is suitable for vital sign processing circuits, especially for radar systems.