This repository is a branch of the caravel_user_project repository, modified for the tapeout of a 512-LUT4 FPGA generated using PRGA.

A 512-LUT4 FPGA generated using PRGA (Princeton Reconfigurable Gate Array)

• An 8x8 array of CLBs, each containing 8 LUT4s and 8 DFFs and a local programmable crossbar for intra-CLB routing
• 24-track routing channel with L1 tracks with cycle-free routing(published at FPL'20, paper.pdf)
• Capable of implementing 16 out of 30 ISCAS'89 circuits

• 1x Caravel user project wrapper
  • 1x PRGA top
    • 64x CLB tile

CLB tile is first synthesized, placed, and routed into a hard macro. The macro routes up to met2 and contains a customized met2 PDN that drives the standard cell power rails.

The PRGA top is then synthesized, placed, and routed as the top-level caravel user design. The PRGA top module contains 64 CLB tile instances and other synthesizable logic. The CLB macros are manually placed in a 2-dimensional array, in which the physical location of each CLB matches the logical location. The switch boxes and configuration circuitry are flattened and synthesized under timing constraints.

The CLB tile uses a customized met2 PDN that drives the standard cell power rails.

The PRGA top adds an additional met3 PDN over the CLB tiles to connnect the CLB tiles' local PDN to the global PDN which is on met4/met5. This is also the key factor in determining the size/shape of the CLB tile as well as the horizontal/vertical spacing between CLB tiles.