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Open MPW Projects

Ibtida_II public

Zeeshan Rafique

This submission is for Ibtida-I which was selected for the First MPW Shuttle. Due to the issues...

caravel_iiitb_bidicntr public

PANKAJ AGRAWAL | http://www.vlsisystemdesign.com/

This project is about 8 bit bidirectional counter which s controlled by control signal. As name...

iiitb_sfifo public

Anmol Shetty | https://www.vlsisystemdesign.com/

This project simulates a synchronous FIFO where data is written in a sequential manner into a...

unigate-sky public

Tamas Hubai

Universal logic gates, self-documenting version

Modified Baugh... public

Aditya Nagaraj | https://rvce.edu.in

8 bit modified fixed point baugh wooley multiplier, following Q5.3 representation

iiitb_sqd_1010 public

Anuj Kumar Jha | https://www.vlsisystemdesign.com/

In this project, Mealy based non overlapping sequence detector is implemented to detect 1010...

8 bit Priority Encoder public

Siddharth

It Encode data Our priority vice

FABulous_Sky public

Nguyen Dao

Demonstration of the Fabulous FPGA design flow using the Skywater 130 process. The design...

IIITDMK_16-point... public

Praneeth | https://www.iiitdm.ac.in/

Implementing the matrix operation of 16-point Walsh Transform using 8-bit inputs.

Game of Life Cell public

Uri Shaked

Implements the logic of a single game of life cell

universal-shift-register public

Subash Polisetty

Register which performs various options based on a control input

gbcart public

Maximilien Dagois

Mask ROM of a game boy sample + LFSR for use on address 0x2001 to 0x20FF.

IIITDMK_pro_row_i... public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

pro_row_idct_folded

grey_codes public

Daniel J Wisehart

Basic grey counter.

Current Starved... public

NALINKUMAR S | https://www.vlsisystemdesign.com/

This project focuses on design of a Current Starved VCO using Google Skywater (sky130)...

AS2650 public

Luca Horn

Replica of the long abandoned and forgotten S2650 8-bit architecture. Only implements a subset...

iiitb_uarttx_mpw8 public

Jay shah | www.vlsisystemdesign.com

This project simulates the designed UART Transmitter module which is used to transmit a data...

synth_test public

Benoit Callebaut

Nest generation audio synthetizer engine

General_Purpose_B... public

Anmol Purty | https://www.vlsisystemdesign.com/

A General Purpose Bandgap Reference IP block that generates constant voltage at output, which is...

ISA 16-bit Microprocessor public

Aloke Das

This is simple microprocessor. Instruction Set Architecture (ISA). The data bus is 16 bits wide....

iiitb_vm public

Siddhant Nayak | https://www.vlsisystemdesign.com/

In this project, a vending machine with change system using Verilog HDL is proposed based on...

PRGA-test public

Sam Lim

An initial attempt to create a Test chip

Graphics Controller public

Vijayan Krishnan | https://www.chipwaretechnologies.com/

The openGFX430 is a synthesizable Graphic controller written in Verilog and tailored for the...

patmos_final_test public

Luca Pezzarossa

Test of new patmos

Two Stage CMOS... public

Madhuri Hemant Kadam | http://www.vlsisystemdesign.com/

CMOS OPAMP is Basic building block of analog and Mixed signal circuits. It is used in many...

Waveform Generator public

Leo Moser | https://www.semify-eda.com

A generic waveform generator divided into stimulus and driver units that can be arbitrarily...

ReRAM_crossbar public

Soumil Jain | https://isn.ucsd.edu/courses/beng207/

ReRAM 16x16 array characterisation, including forming, incremental set and reset, and parallel...

Systolic Array... public

Ian Zhang

Systolic Array is a classical architecture that is recently revitalized among Neural Network...

RocketAlpha public

Nguyen Dao

This project demonstrates a customized Rocket Chip SoC, generated from Chipyard. The SoC is...

Riscduino-SCore(S4) public

Dinesh Annayya

Arduino pin compatible Single RISCV 32 Bit core Project

caravel_jacaranda-8_GF180 public

Cra2yPierr0t | https://cpu-dev.github.io

PicoRV & Jacaranda-8 - It's a hobby heterogeneous processor!

ButtiChip01 public

ぶっちー ゆっくり | https://www.himasugirubutti.com

チップ欲しい

mips32_processor public

aju narayanan | https://www.bits-pilani.ac.in/hyderabad/

a simple 16 instruction microprocessor

YONGA-CAN Controller public

Abdullah YILDIZ | https://yongatek.com/

YONGA-CAN Controller is a partial implementation of CAN 2.0B standard.

Bitcoin Mining Asic public

Constantine Mantas

This ASIC takes as an input the header of a Blockchain and simulates the bitcoin mining process.

ReRAM-Controller-MPW7_v2 public

Po-Chun Huang | https://ece.umd.edu/

This project contains array of various sizes of 1T1R devices and a 1T1R 256x256 ReRAM module for...

Analog Frontend... public

Simon Waid | https://www.oeaw.ac.at/en/hephy/

This is a simple analog fronted for particle detection. The user may attach a particle detector...

iiitb_cps public

Ishan Desai | https://www.vlsisystemdesign.com/

ASIC Design of Car Parking System.

FABulous_eFPGA public

Nguyen Dao

Demonstration of the open FABulous eFPGA using the OpenLane flow.

Sziklai Pair Amplifier public

SUMANTO KAR | https://www.vlsisystemdesign.com/

This project focuses on design of a Sziklai Pair Amplifier using Google Skywater (sky130)...

In memory computing... public

Deepak verma | https://home.iitd.ac.in/

SRAM in memory computing : The project includes SRAM In Memory Computing Accelerator.

SoomRV public

Mathis Salmen

SoomRV is a simple superscalar Out-of-Order RISC-V microprocessor. It can execute 4 Instructions...

FPGA_Programming_... public

Allen Boston | https://github.com/lnis-uofu

User project wrapper includes the PMU version 3, SOFA 2x2 FPGA generated using OpenFPGA, and...

Riscduino-DCore(D3) public

Dinesh Annayya

Riscduino is a Dual 32 bit RISC V based SOC design pin compatible to arduino platform and this...

HyperRAM controller public

Paweł Sitarz

Project instantiates HyperRAM controller for external memory chip (8MB version) connected to...

TestAsyncTrimux-MPW8 public

Alexander Shabarshin

This is a test circuit for 3-rail async ternary selector that connects one of the 3 ternary...

iiitb_bcdc public

Sritam Birtia | https://www.vlsisystemdesign.com/

The main goals of this project are implementing an 8-bit bcd code counter in skywater 130nm and...

IIITDMK_pro_row_i... public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

pro_row_idct_parallel

IIITDMK_16-bit-Ha... public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

Implementation of 16-bit-Han-Carlson Adder, a parallel prefix fast adder using Sky130nm PDK.

TinyTapeout SkullART public

Uri Shaked | https://tinytapeout.com

Re-run of TinyTapeout 02 with an extra SkullART slot

iiitb_jc public

Aman Prajapati | https://www.vlsisystemdesign.com

A Johnson counter is a modified ring counter in which the output from the last flip flop is...

GWU MPW8 Verification public

Joseph Riem

GWU's project to verify gds file using efabless precheck and tapeout check.

IIITDMK_16-bit-La... public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

Implementation of 16-bit-Ladner-Fischer-Adder, a parallel prefix fast adder using Sky130nm PDK.

caravel_iiitb_lfsr public

ritesh lalwani | https://www.vlsisystemdesign.com/

The Aim of this exercise is to design a linear feedback shift register to produce a random...

GF180_SSD public

Nishad Potdar

This is an implementation of BCD to Seven Segment Decoder. The module takes 4 bit BCD input and...

iiitb_gc_mpw8 public

Tejas B N | https://www.vlsisystemdesign.com/

Gray code counter is a digital counter that counts such that each successive bit patterns...

Hardened_ALU public

Janani Aravind

Radiation Hardened ALU

clock_divide_selector public

Takuya Sasatani | https://www.takuyasasatani.com/

Generates multiple clocks and outputs the selected clock

Yatsuhashi (MPW7) public

Yukidamayaki

Resubmission

iiitb_tlc_mpw8 public

LOKESH MAJI | https://www.vlsisystemdesign.com/

In this project, traffic light controller on a four-way road using a sensor is proposed. A...

pwm_gen public

Himanshu Rai | https://www.vlsisystemdesign.com/

this project is about pwm generator with a feature of variable duty cycle .

iiitb_lifo public

Yash Kothari | https://www.vlsisystemdesign.com/

LIFO buffers are a contiguous piece of memory that require special methods to add and remove data.

iiitb_brg public

| vlsisystemdesign.com

Chip for Baud Rate Generator

3bit_rc public

Arsh Kedia | https://www.vlsisystemdesign.com/

3 bit ring counter

SequenceDetection public

Paras Vekariya

This project simulates the overlapping Moore Design for Sequence Detection where it toggles the...

Zero to ASIC... public

Matt Venn | https://www.zerotoasiccourse.com/

Zero to ASIC course group submission for MPW8

RRAM_IMC_MPW8 public

Chithambara Moorthii J

The project includes RRAM In Memory Computing Accelerator , designed by our team at IIT...

Hash Accelerator... public

Abdul Moiz Sheikh

The project aims to deliver a dual mode hashing accelerator which is capable of high speed...

FABulous on GF180 public

Myrtle Shah

FABulous eFPGA fabric generated and taped out on the new gf180 process

Rift2Go_2300_GF180_MPW0 public

Ruige Lee

This is the simplest version of Rift2Core. Rift2300 has no L2 cache, no L1 ICache, no L2 TLB, no...

OneHot FABulous... public

Myrtle Shah

FPGA based on FABulous but using an experimental combined custom bitcell+tgate config routing element

IIITDMK_hada_2d1_3 public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

hada_2d1_3

SPI with Clock... public

Abdul Moiz Sheikh

Serial peripheral interface (SPI) is one of the most widely used interfaces between...

iiitb_bc _caravel public

Ujjawal Sharma | https://www.vlsisystemdesign.com/

A bidirectional counter is a sequential up/down That has the ability to count in both directions...

IIITDMK_mcm_8outputs public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

mcm_8outputs

iiitb_sipo_mpw8 public

ADITYA SINGH | https://www.vlsisystemdesign.com/

serial in parallel out shift register

IIITDMK_16-bit-Ko... public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

Implementation of 16-bit-Kogge-Stone-Adder, a parallel prefix fast adder using Sky130nm PDK.

iiitb_4bbc public

Sahil Mahajan | www.vlsisystemdesign.com

Physical Design of a 4 bit bidirectional counter

IIITDMK_97... public

Praneeth | https://iiitdm.ac.in/

Conventional lifting based 9/7 DWT using direct implementation.

IIITDMK_32-point... public

Praneeth | https://iiitdm.ac.in/

32-point proposed Integer DCT using parallel architecture, odd_even_parallel_complete

iiitb_wm public

Archan Desai | https://www.vlsisystemdesign.com/

ASIC design of automatic washing machine

openram_testchip_mpw8 public

Jesse Cirimelli-Low | https://vlsida.soe.ucsc.edu/

This testchip includes various SRAM designs generated with OpenRAM, an open srouce memory...

yifive_a2 public

Manikanta | https://univisiontechnocon.com/

RISC-V based sub system

Riscduino-SCore(S3) public

Dinesh Annayya

Arduino pin compatible Single RISCV 32 Bit core Project

IIITDMK_53... public

Praneeth | https://iiitdm.ac.in/

Conventional 13X13 proposed N-parallel (5,3) lifting based 2D DWT

tiny_user_project... public

Anish Singhani

ASIC implementation of the iconic Beep Boop traffic light at Carnegie Mellon University (also as...

tiny_user_project... public

Thorsten Knoll

The historic arithmetic-logic-unit (ALU) 74181 from the 70's. Pure combinatorial with 4-bit...

TestAsyncTrimux public

Alexander Shabarshin

This is a test circuit for 3-rail async ternary selector that connects one of the 3 ternary...

ChipFlow example... public

Staf Verhaegen

Implementation of ChipFlow example SoC with 3.3V version of the c4m-flexcell standard cells.

gf180_state_machine public

Xuanjia Bi | https://engineering.virginia.edu/high-performance-low-power

This is state machine that monitors water and temperature change in a closed feedback loop.

IIITDMK_mcm_resource public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

mcm_resource

OpenFASOC Test... public

Mehdi Saligane

TBD

iiitb_sd_mpw8 public

Anshul Madurwar | https://www.vlsisystemdesign.com/

Sequence Detector Design

SkullFET GF180 public

Uri Shaked | https://wokwi.com

Barebore transistors

SPELL public

Uri Shaked | https://wokwi.com

SPELL is a minimal, stack-based programming language created for The Skull CTF.

modulador public

susana ortega cisneros | https://unidad.gdl.cinvestav.mx/

Another test of gf180 with a synchronous modulator for another doctoral student in electronic...

OneHot FABulous... public

Myrtle Shah

reduced size version of the one-hot mux fabric

Digital Biquad... public

Tiago Silva

This project contains a digital IIR biquad filter. Adapted from:...

IIITDMK_integer_mcm public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

integer_mcm

Fuzzy Wavelet GF180 public

Opensource FoodRev Projects

Wavelet Transform with pre-filters

RISCV with CNN... public

Asma Mohsin | https://tinytapeout.com

Convolution Neural Network co processor is added with RISCV to enhance the performance of...

Serv-tri-core public

Greg Davill

An award winning serial RISCV SoC from Olof Kindgren. This project incorporates 3 separate...

EduWave public

Ryan Matthew Price | https://www.utep.edu/engineering/ece/

Experimental Digital Process Blocks for Incomplete PDK

alu_paper_gf180 public

Emilio Baungarte | https://unidad.gdl.cinvestav.mx/

Testing an ALU using gf180 technology, to support a recently submitted journal article titled,...

16x4 bit dual... public

Rolf Widenfelt

16x4 bit dual port register file, with dual read ports and a single write port - perfect for the...

modulador_a public

luis adolfo luna | https://unidad.gdl.cinvestav.mx/

Test of gf180 with an asynchronous modulator, which is part of a PhD project at Cinvestav in...

fastmul_16x16 public

Hari V

fastmul_16x16

Carry_Look-Ahead_Adder public

Vrushabh Damle

This is an implementation of a 4-bit carry look-ahead adder which is a fast adder. It has two...

fastmul_32x32 public

Hari V

fastmul_32x32

Rift2Go_2300_Sky130_MPW8 public

Ruige Lee

This is the simplest version of Rift2Core. Rift2300 has no L2 cache, no L1 ICache, no L2 TLB, no...

uqab public

Waleed Waseem

uqab is an SoC.

IIITDMK_accumulat... public

Praneeth | https://iiitdm.ac.in/

Conventional accumulator based 2D parallel architecture (N-outputs at a time), area and...

Low Power... public

Ali Sabir | http://isb.nu.edu.pk/rfcs2/

A low power approximate processor for IOT intelligent edge nodes applications. The proposed...

decrypt_aes128 public

Uriel Jaramillo Toral | https://unidad.gdl.cinvestav.mx/

Decrypt AES 128, using skywater 130nm technology, which will serve as part of a master's thesis...

BFG 4-LUT Test public

Arya Reais-Parsi | https://eecs.berkeley.edu

Stamps out BFG-generated 4-LUTs to measure their performance.

GF180MCU Test... public

Philipp Gühring | https://libresilicon.com/

Automatically generated Test Structures with the DanubeRiver Tool, to test the Global Foundries...

ISA 16-bit... public

Aloke Das

This is simple microprocessor. Instruction Set Architecture (ISA). The data bus is 16 bits wide....

Cryptographically... public

RECEP GÜNAY

Cryptographically Secure RNG Design. (MPW6 resubmission)

Universal Shift Register public

Subash Polisetty

8-bit Universal Shift register that performs various operations based on a control input

Asicle rollover public

Tamas Hubai

Have you played Wordle on raw silicon yet? (This is a resubmission from MPW5.)

RHBD_ALU_GF180 public

Janani Aravind

ALU-Radiation Hardened By Design

Stu154 F22... public

Anish Singhani

A group submission including several small designs contributed by students at Carnegie Mellon in...

GF180 VGA Clock public

Matt Venn | https://zerotoasiccourse.com

My VGA clock rehardened for GF180

riscduino pxt1 public

Dinesh Annayya

Riscduino Peripheral Extension Chip Set-1

Deprecated -... public

Zexi Liu | https://www.cmu.edu/

This project aims to build multi-purpose characterization on-chip instruments using the...

SSD_MPW8 public

Nishad Potdar

This is an implementation of BCD to Seven Segment Decoder. The module takes 4 bit BCD input and...

usb2uart-mpw8 public

Roman Bacik

USB to UART converter

UCSC OpenRAM Test Chip... public

Matthew Guthaus | https://vlsida.soe.ucsc.edu/

This project contains a test chip for several OpenRAM memory configurations. The configurations...

GF180MCU-C... public

Philipp Gühring | https://libresilicon.com/

This is a second test-design which provides several automatically generated standard cells...

IIITDMK_16-bit-Sk... public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

Implementation of 16-bit-Sklansky-Adder, a parallel prefix fast adder using Sky130nm PDK.

iiitb_pwm_genn public

Gopala Krishna Reddy Sanampudi | https://www.iiitb.ac.in/

Pulse Width Modulation is a famous technique used to create modulated electronic pulses of the...

fuserisc2 public

Nguyen Dao

Demonstration of the Fabulous FPGA design flow using the Skywater 130 process. This project...

ICESOC public

Nguyen Dao

Ibex Crypto eFPGA SoC

Pyramiden Core public

Brown Deer Technology | www.browndeertechnology.com

This is a processor design that evolved from a tiny tapeout submission. The core implements a...

GF180 Pulse... public

James Tandon | https://www.csueastbay.edu

A basic pulse with modulation core with 8 PWMs controled by a wishbone bus slave interface. The...

FABulous_eFPGA_wb public

Nguyen Dao

This project demonstrates open source eFPGA generated by FABulous. This version is to support...

IIITDMK_16-bit-Br... public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

Implementation of 16-bit-Brent-Kung-Adder, a parallel prefix fast adder using Sky130nm PDK.

Comparator and... public

Harry Snell

3v3 comparator with 1v8 output. For possible future uses in ADCs. May also include other related...

Subservient-MPW4 public

Klas Nordmark

An ASIC-adapted version of the award-winning bit-serial RISC-V processo SERV, resubmitted due to...

RRAM_testchip public

Nguyen Dao

This submission is to test rram and its programming circuit using for eFPGA

Mixed_signal_circ... public

Carl L Brando | https://umd.edu/

We have a 2x2 1T1R ReRam structure and a C4 Filter as well as some other supporting analog...

iiitb_tlc public

Maurya Patel | https://www.vlsisystemdesign.com/

A Traffic light controller made using sky130 technology node. Traffic lights are signaling...

iiitb_rv32i public

Vinay Rayapati | https://www.vlsisystemdesign.com , https://www.iiitb.ac.in

This project provides an insight into the working of a few important instructions of the...

GreenRio_GF_Version public

yinguohua | rioslab.org

a greenrio1.0 gf180 version

LABS Search public

Wouter van Verre

An accelerator core for finding binary sequence with low autocorellation values

sky130CLA public

Vrushabh Damle

This is an implementation of a 4-bit carry look-ahead adder which is a fast adder. It has two...

azadi_soc_ibex public

Zeeshan Rafique | https://www.linkedin.com/company/merluit

Azadi is an SoC with a 32-bit RISC-V signal core extended version of ibex we named it "buraq",...

iiitb_usr public

Debangana Mukherjee | https://www.vlsisystemdesign.com/vsd-iat/

4-bit Universal Shift Register

MicroMotorSequencer public

Joshua Stevens

A phased PWM controller for micro motor control

webinar_test_1 public

Marwan Abbas

SPM example user project

Mixed-Signal SoC... public

Sepide Asgari

Nanopore-based DNA sequencing is a unique, scalable technology, utilized to identify nucleotides...

rvj1-caravel-soc-mpw7 public

Jure Vreča | https://github.com/jurevreca12/rvj1-caravel-soc-mpw7

A simple SoC using the custom riscv-jedro-1 processor design.

IOTestVehicle public

Staf Verhaegen

Test chip for higher speed IO pad cells

5bitsMulti-gf180 public

Jorge Angarita Pérez

A custom 5-bit multiplier

AI-CHIP-4-IN-1 public

김태현 | https://github.com/thkim2031

In this chip there are four macros : 1. b-float FMA (16bit multiplication and 32bit...

Memory array public

Binoy B

Implementation of an 8x64 memory array

My First EF ASIC public

Larry Pearlstein | http://pearlstein.pages.tcnj.edu

Retarget FPGAs to standard cell.

GF180 Russell public

Russell Friesenhahn

Matt Venn's famous VGA clock with SPI control

Radix-2 4-bit... public

Yashwant Moses | vsdiat.com

Booth's Multiplier is based on Booth's Multiplication Algorithm. It proposes an efficient way...

Co-Processor-with... public

Abdul Moiz Sheikh

The aim of project is to design a co-processor for floating point arithmetic and encryption...

Nanofabrication... public

Mehdi Saligane

Test Structures for NIST's Nanofabrication Project

Fitbit Project... public

Mehdi Saligane

Test harness for MEMS sensing

Caravel public

Lena Hwang

A template SoC for Google sponsored Open MPW shuttles for SKY130

iiitb_ptvm public

| https://www.vlsisystemdesign.com

A parking ticket vending machine based on FSM, implemented using verilog.

TinyRocket_SoC public

Nguyen Dao

This project demonstrates an customized TinyRocket SoC, generated from Chipyard. The SoC is...

YatCPU public

Howard Lau

This is a standalone educational RISC-V CPU, capable of running a Tetris game!

LeoSoC public

Leo Moser

A very simple SoC

iiitb_pipo_mpw8 public

priyanshu | https://www.vlsisystemdesign.com/

Shift registers are some sort of sequential logic circuitries that are majorly deployed to store...

IIITDMK_53... public

Praneeth | https://iiitdm.ac.in/

DWT - Conventional 5/3 lifting based wavelet with 3 octaves.

IIITDMK_dct_8 public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

dct_8

Counter project public

Anirudh Sivaraman

Test project with minimal changes to caravel_user_project

Mixed_signal_circ... public

Carl L Brando | https://www.umd.edu

We are planning to make a Mixed signal in-memory compute ReRAM arrray. This takeout will allow...

SRAM_IMC_MPW8 public

Deepak verma | https://home.iitd.ac.in/

SRAM in memory computing : The project includes SRAM In Memory Computing Accelerator. This is...

mpw-8-as1x00 public

Luca Horn

First attempt at a Microcontroller, featuring a 4-bit CPU with re-programmable microcode....

IIITDMK_dct_16 public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

dct_16

ReRAM Devices... public

Po-Chun Huang | https://ece.umd.edu/

This project contains array of various sizes 1T1R and stand-alone ReRAM test structures for...

IIITDMK_biquad_iir_ext public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

biquad_iir_ext

gf180_vs_sky130 public

Uriel Jaramillo Toral | https://unidad.gdl.cinvestav.mx/

This is the comparison project of the projects of the CINVESTAV GUADALAJARA community. The...

Riscduino-pxt1 public

Dinesh Annayya

This is chip is add-on to our Riscduino SCORE/DCORE/QCORE Chip set. As there are no free space...

SLOCI_Resubmission public

Zexi Liu | www.cmu.edu

SKYWATER Lab-on-chip IC resubmission. This project aims to build multi-purpose characterization...

iiitb_freqdiv public

Dantu Nandini Devi | https://www.vlsisystemdesign.com/

This is a model of a Freqency Divider. This model will contain a 4 bit number lines to select by...

iiitb_rc public

Kavya Agarwal | https://www.vlsisystemdesign.com/vsd-iat/

Ring Counter

mpw7 walkthrough public

Matt Venn

mpw7 walkthrough

GF180MCU-C... public

Philipp Gühring | https://libresilicon.com/

This is a test-design which provides several automatically generated standard cells directly...

SLOCI2 public

Zexi Liu

Lab-on-chip test IC

S3GA public

Jan Gray | http://fpga.org

S3GA: simple scalable serial FPGA. An area-efficient hierarchical FPGA core with serial logic...

Hyperspace-resubmission public

Vladimir Milovanović | www.novelic.com

A hybride parameterizable radar signal processing accelerator

Fast GCD for... public

Kavya Sreedhar

Computes the Bezout coefficients associated with 1024 bit numbers with a GCD of 1.

iiitb_rtc public

BANDA ANUSHA | https://www.vlsisystemdesign.com/

Real-Time Clock

ppcpu public

Piotr Wegrzyn

Pipelined 16 bit cpu with custom architecture

RVcore Chip1 public

Kenji Kise | https://www.arch.cs.titech.ac.jp/

Design a five-stage pipelining processor of RISC-V RV32I

Patmos MPW7 public

Martin Schoeberl | https://github.com/os-chip-design/os-chip-design

The Patmos processor. A one-semester project with 12 students at the Technical University of...

IIITDMK_dct_4 public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

dct_4

IIITDMK_DCT4_PAR_2D public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

DCT4_PAR_2D

IIITDMK_DWT... public

Praneeth

Conventional convolution based folded DWT using Recurse 46, 32-bit Wallace tree multiplier

Project-Yatsuhashi public

Yukidamayaki | analogmiko.com

RF Magic

ReRAM-Controller-MPW7 public

Po-Chun Huang | https://ece.umd.edu/

This project contains array of various sizes of 1T1R devices and a 1T1R 256x256 ReRAM module for...

IIITDMK_IIR-Filte... public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

IIR-Filter-using-Baugh-Wooley-Multipler

IIITDMK_dct4_par_2d public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

dct4_par_2d

eFPGA_4X4_MPW8 public

Emilio Baungarte | https://unidad.gdl.cinvestav.mx/

eFPGA_4X4_MPW8

IIITDMK_dct8_par_2d public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

dct8_par_2d

IIITDMK_radix2_parallel public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

radix2_parallel

IIITDMK_iir2_direct public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

iir2_direct

Caravel PyFive public

Maximo Balestrini

Peripherals tests for future SoC targeting Micro/Circuit Python

Shalicon public

hezixu

A fork from SoomRV-8

IIITDMK_DWT... public

Praneeth | https://iiitdm.ac.in/

Conventional convolution based folded DWT using Recurse 35 and 32-bit Wallace tree multiplier

IIITDMK_DCT_4 public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

DCT_4

64-Bit Adder public

Kerem Can Balı

64-Bit 2 Number - calculator

IIITDMK_dct4_2d public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

dct4_2d

Potentiometric_10bit_DAC public

Sameer S Durgoji | https://www.vlsisystemdesign.com/

Design of a 10 Bit Potentiometric Digital to Analog Converter with 3.3V analog voltage, 1.8V...

IIITDMK_iir2_1multi_ext public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

iir2_1multi_ext

unigate-gf public

Tamas Hubai

Implement any combinatorial logic on 4 inputs by wiring up the pins the right way

Crypto Accelerator V3 public

Anish Singhani

Third iteration of open-source cryptography core implementation

hehecore public

Yifei Zhu | https://rioslab.org/

We come from RIOS Lab, TsingHua university, we designed a 64-bit dual-issue, out-of-order RISC-V...

Smart Glove public

YERRA BHASKARA VARA PRASAD

The smart glove transforms the hand signals to text and to speech by utilizing Arduino voice...

Caravel_SHA3 public

Furkan Ciylan

Implementation of SHA 3 Encrytion algorithm on caravel using skywater 130nm technology.

IIITDMK_dct8_2d public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

dct8_2d

IIITDMK_iir6_multi_ext public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

iir6_multi_ext

reram_module_mpw8 public

Po-Chun Huang

This project contains array of various sizes of 1T1R devices and a 1T1R 256x256 ReRAM module for...

Sky130 Test... public

Philipp Gühring | https://libresilicon.com/

Test Structures for Sky130 generated by DanubeRiver

IIITDMK_16-point... public

Praneeth | https://www.iiitdm.ac.in/

Implementing the matrix operation of 16-point Hadamard Transform using 8-bit inputs.

IIITDMK_iir6_cascade public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

iir6_cascade

IIITDMK_iir6_direct public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

iir6_direct

IIITDMK_iir6_multi_delay public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

iir6_multi_delay

ReRAM based CNN... public

Talha Bin Azmat | http://isb.nu.edu.pk/rfcs2/

This project consists of a DNN accelerator which used cross bar array to perform in-memory...

tiny_user_project... public

Thorsten Knoll

Hardware circuit with an VGA output that displays a simple clock on the screen.

IIITDMK_six_iir_ext public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

six_iir_ext

HyperRAM... public

Paweł Sitarz

Project instantiates HyperRAM controller for external memory chip (8MB version) connected to...

Coriolis Test... public

Myrtle Shah

VexRiscv+SPI flash+HyperRAM SoC built using Coriolis & PDKMaster - WIP designed to be...

rvce_serial-adder public

MAKAM MANIKYA RAKSHITH

Serial Adder

ReRAM block public

Barak Hoffer

ReRAM block

SumMult5_3_GF180 public

Nicolás Orcasitas Garcia

Small digital circuit that calculates the sum of the multiples of 3 and 5 until a previously...

Wishbone PIO public

Sean "xobs" Cross

Wishbone PIO is an implementation of the PIO block attached to the Wishbone bus. A PIO block is...

My_Proj public

Karthikeyan R

Nahh

ReRAM Array Test public

Lekan Afuye

Full ReRAM Memory banks

Swayambhu RISC processor public

MUKUL LOKHANDE

RISC based procesor

rvj1-caravel-soc public

Jure Vreča | https://github.com/jurevreca12/

Integrates the riscv-jedro-1 processor into a very simple system-on-a-chip design.

CMOS... public

Maher Benhouria

A simple rail-to-rail comparator with its bias circuitry to test the SKY130 analog design flow.

Approximate Adder AXHA public

S Skandha Deepsita

This project is an implementation of approximate adder for error tolerant multimedia...

iiitb_alu public

AASHISH TIWARY | https://www.vlsisystemdesign.com/

Arithmatic Logic Unit ALU is a processor unit which performs the task of addition, subtraction,...

ReRAM crossbar rerun public

Soumil Jain | https://isn.ucsd.edu/courses/beng207/

ReRAM 16x16 array characterisation, including forming, incremental set and reset, and parallel...

SoomRV (MPW-8) public

Mathis Salmen

SoomRV testing resubmission for MPW-8!

iiitb_usr_mpw8 public

Rakshit Bhatia | https://www.vlsisystemdesign.com/

The universal shift register features parallel load, left-shift and right-shift serial input,...

Ariel eFPGA public

Alexander Monakhov | https://engineering.phys.msu.ru/en/

This is a part of Uranus FPGA project. Our goal is to create open source configurable FPGA...

8x_PLL_Clock_Multiplier public

Subham Mohapatra | https://www.vlsisystemdesign.com/

8x PLL Clock Multiplier. Input frequency ranges from 5MHz to 12MHz and output frequency is from...

SequenceDetection1010 public

Paras Vekariya | VSD-IAT

This project simulates the overlapping Moore Design for Sequence Detection where it toggles the...

PISO(Parallel... public

Raj kachhadiya | www.vlsisystemdesign.com

The information stored within these registers can be transferred with the help of shift...

space_shuttle public

Ahmad Nofal

small summary never hurts

Asicle public

Tamas Hubai

Have you played Wordle on raw silicon yet?

Test Chip 0 -... public

Russell Friesenhahn | https://www.utexas.edu/

This project demonstrates a butterfly for an FFT with options to receive data from an external...

iiitb_elevator_controller public

Nishit Chechani | https://www.vlsisystemdesign.com/

The project below illustrates how an elevator controller can be designed for as many floors as...

Efabless processor public

Andrew Feldman

Basic design to familiarize with this service

Libre-SOC Crypto-Router public

Luke Leighton | http://libre-soc.org

Libre-SOC is an entirely Libre-licensed SoC based on the OpenPOWER v3.0 ISA. Layout is in...

clusterv_soc_mpw2 public

Matthew Ballance

Quad-core RISC-V SoC with on-chip memory and peripherals

OsciBear public

Dan Fritchman

Berkeley student-designed wireless SoC, featuring a RISC-V Rocket processor, hardware AES...

ChristmasTreeCont... public

Julien OURY

Christmas tree controller (MPW5 ReRun)

UETRV_ESoC_v2 public

Muhammad Usama Zubair | https://github.com/ee-uet

Slightly modified version of UETRV_ESoC, a RISC-V based Embedded class SoC integrating 3-stage...

SAR-ADC and... public

Harald Pretl | https://iic.jku.at

We have implemented mixed signals blocks: A SAR-ADC with 12b and OSR=1...256 (decimation filter...

Kasirga K0 public

İsmail Emir Yüksel | http://www.kasirgalabs.com/

RISC-V SoC

SuSoC1 public

Aedan Cullen

`

Caravel_FPU public

Komal Javed | https://lampromellon.com/

Caravel_FPU integrates floating point unit with Caravel Core. It is capable of doing floating...

pifive-soc public

Anish Singhani

RISC-V SoC

SRAMTestVehicleSequel public

Staf Verhaegen

Iteration on SRAM test vehicle that was not selected for MPW5.

PLL-based... public

Jorge Marin

Time-based capacitive sensor interface using highly-digital custom building blocks

test digital precheck public

Chithambara Moorthii J

test for precheck digital

MSSRO_based_VCRO public

ANCHIT PROCH

A high-performance, separately driven, noise-canceling, skew-based Voltage Controlled Ring...

SonaronChip-8 public

Mauricio Alejandro Montanares Sepúlveda

process acoustics signals from 8 MEMS microphones with an extended frequency range up to 85 kHz...

Chameleon SoC public

M. Shalan | http://efabless.com

AHB-Lite based SoC for IBEX

VerilogBoy public

Wenting Zhang

VerilogBoy Game Console SoC

VSDMemSoC public

Mufutau Akuruyejo

VSDMemSoC is a small SoC including a RISCV-based processor named RVMYTH and an external 1kB SRAM...

Coriolis Test SoC -... public

Myrtle Shah

Test SoC using Amaranth; Coriolis; PDKMaster for MPW4

caravel_dsc public

Raj Babu

Caravel Harness based Digital Signal Controller for Embedded Control applications , the user...

Rivest Cypher 4 public

RAHUL SREEKUMAR | https://engineering.virginia.edu/high-performance-low-power

The Rivest Cypher 4 is a stream cipher algorithm developed in the 1980s, remarkable for its fast...

SHA1 engine public

Konrad Rzeszutek Wilk

The SHA1 engine, while not the most secure nowadays is still used by git commits and TPM PCR...

game of live... public

Miles Segal

calculates state of cell based on state of neighbors

Space Shuttle GF Node public

Iván Rodríguez Ferrández

The main goal of this project is to assess the reliability of the Global foundries 180nm...

Test_pcheck public

KSHITIZ TYAGI

Testing precheck

Space_Shuttle public

Iván Rodríguez Ferrández | https://www.bsc.es

The main goal of this project is to assess the reliability of the SkyWater 130nm manufacturing...

FuseRISC public

Andrew Attwood | https://github.com/andrewattwood/fuserisc.git

FuseRISC will demonstrate the benefits of the tight coupling of RISC-V cores and eFPGA fabric...

I2C Controller public

Karthik Mahendra

I2C bus controller transmits 8-bit serial data to multiple targets

VSDBabySoC public

Mufutau Akuruyejo | httpS://WWW.vlsisystemdesign.com

VSDBabySoC is a small SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.

Bandgap_Reference_Design public

Swarup Pulujkar | https://www.vlsisystemdesign.com

A Bandgap Reference Circuit To Generate A Constant Voltage Output That Is Insensitive To...

Rift2Fake public

Ruige Lee

This is a Fake Rift2Core. There is a LFSR and Multiplier in it!

riscduino-R1 public

Dinesh Annayya

A arduino pin compatible RISC V Project

SRAMTestVehicleG4 public

Staf Verhaegen

Iteration on SRAM test vehicle that failed to be selected for MPW5, MPW6 and MPW7.

rift2fake_test_gf180_MPW0 public

Ruige Lee

There is a LFSR in it.

Christmas tree... public

Julien OURY

Christmas tree controller (MPW5 ReRun)

Riscduino-DCore(D4) public

Dinesh Annayya

Riscduino is a Dual 32 bit RISC V based SOC design pin compatible to arduino platform and this...

SoC_Now public

MERL SoC-Now | https://github.com/merledu

This SoC is generated by the SoC Now Generator. It is written in Chisel.

sequence detector public

RAVI KIRAN REDDY GOGIREDDY | https://www.iiitb.ac.in/. https://www.vlsisystemdesign.com/

detecting the sequence 10111.

darkriscv in openlane public

Bhawandeep Singh

The project is a realization of darkriscv processor using openlane and skywater pdk. It has a...

riscduino_qcore_folk public

Giter CN

folk of riscduino_qcore for test

AutomaticStandard... public

Philipp Gühring | https://libresilicon.com/

At Libresilicon we have been working for several years on making chipdesign and production...

Riscduino-SCore(S5) public

Dinesh Annayya

Arduino pin compatible Single RISCV 32 Bit core Project

Ophelia eFPGA public

Egor Lukyanchenko

Uranus eFPGA with nonvolatile config in eFuse array.

Rift2Go_2330_Sky130_MPW8 public

Ruige Lee

This is an almost full-functional version of Rift2Core. Rift2330 has the smallest L2 cache, L1...

Caravel HyperRAM... public

Paweł Sitarz

Project instantiates HyperRAM driver for external memory chip (8MB version) and additional...

8-bit SAR-ADC... public

Christoph Weiser

This is a Analog to Digital Converter based on the popular SAR architecture. It has 8-bit...

SAR-ADC and... public

Christoph Weiser

This submission consists of a updated 8-bit SAR-ADC, basic analog support circuitry, such as...

Key Value store public

Giray Pultar

Key value store implemented on asic.

Ibtida-II public

Merl Uit

This submission is for Ibtida-I which was selected for the First MPW Shuttle. Due to the issues...

Caravel Plus public

M. Shalan | http://efabless.com

Caravel management SoC attached to the largest possible SRAM that can fit the user's area.

Four-Bit ALU_XOR - MPW-6 public

Janani Aravind | https://www.ncat.edu/

This is a digital 4-bit ALU_XOR design.

Space Controller public

Iván Rodríguez Ferrández

This design is a radiation tolerant UART server that can be used for low level control of...

Caravel_RISCV_OSU public

James Stine | https://vlsiarch.ecen.okstate.edu/

Caravel_RISCV_OSU is an implementation of a single-cycle RISC-V processor inside of the Caravel...

FWPayload public

Matthew Ballance | http://github.com/mballance

A simple RISC-V core+peripherals subsystem for the Google-sponsored Open MPW shuttles for SKY130.

caravel_periphera... public

Siva Prasad

A attempt to integrate various peripherals like I2C, I2S, UART, SPI, QSPI , JTAG, PWM, GPIO ,...

io_expander public

Siva Prasad

A gpio expander for the caravel harness to realize a small microcontroller

crypto_aes128 public

Uriel Jaramillo Toral | https://unidad.gdl.cinvestav.mx/

AES128 project test

1V8 LDO Design... public

Amro Tork | https://mabrains.com

1V8 LDO Design in Skywaters 130nm

Class-D Audio Amplifier public

Hongzhe Jiang

This project is intended to implement a closed-loop class-d audio amplifier with 1.8 V power...

SORIC public

Thinh Pham

A SoC with two crypto-supported RISC-V cores.

ASIC Design of... public

Uzair Ahmad | http://isb.nu.edu.pk/rfcs2/

Space application Integrated Circuits (ICs) are prone to radiation particles, which are present...

CMOS Frequency... public

Adithya Sunil Edakkadan

2.87 GHz frequency synthesizer with programmable sweep.

APPROXIMATE Multiplier public

Rana Muhammad Shahid Jamil | http://isb.nu.edu.pk/rfcs2/

This project implements an approximate multiplier for image processing applications

Lexicon public

Wajeh

This Is A Machine-Mode (M-Mode) Only, 32-Bit Cpu Small Core Which Supports Risc-V’s Integer (I),...

Delta-Sigma... public

Harald Pretl

As a classroom project at Johannes Kepler University, we are designing a delta-sigma audio DAC,...

Azadi_III public

Rameen Anwar | https://github.com/merledu

This project is the extended version of Azadi-SoC, which includes all of the peripherals which...

Sky130 RadTol Test Chip public

Javier Contreras

Test structures for the study of ionizing radiation tolerance in the Skywater 130 process.

microcontroller_sensors public

Omar Mohamed Saadawy

Voltmeter & Ammeter