Zeeshan Rafique
This submission is for Ibtida-I which was selected for the First MPW Shuttle. Due to the issues...
PANKAJ AGRAWAL | http://www.vlsisystemdesign.com/
This project is about 8 bit bidirectional counter which s controlled by control signal. As name...
Anmol Shetty | https://www.vlsisystemdesign.com/
This project simulates a synchronous FIFO where data is written in a sequential manner into a...
Anuj Kumar Jha | https://www.vlsisystemdesign.com/
In this project, Mealy based non overlapping sequence detector is implemented to detect 1010...
Aditya Nagaraj | https://rvce.edu.in
8 bit modified fixed point baugh wooley multiplier, following Q5.3 representation
Siddharth
It Encode data Our priority vice
Nguyen Dao
Demonstration of the Fabulous FPGA design flow using the Skywater 130 process. The design...
Subash Polisetty
Register which performs various options based on a control input
Uri Shaked
Implements the logic of a single game of life cell
Maximilien Dagois
Mask ROM of a game boy sample + LFSR for use on address 0x2001 to 0x20FF.
Praneeth | https://www.iiitdm.ac.in/
Implementing the matrix operation of 16-point Walsh Transform using 8-bit inputs.
Daniel J Wisehart
Basic grey counter.
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
pro_row_idct_folded
Luca Horn
Replica of the long abandoned and forgotten S2650 8-bit architecture. Only implements a subset...
Jay shah | www.vlsisystemdesign.com
This project simulates the designed UART Transmitter module which is used to transmit a data...
NALINKUMAR S | https://www.vlsisystemdesign.com/
This project focuses on design of a Current Starved VCO using Google Skywater (sky130)...
Benoit Callebaut
Nest generation audio synthetizer engine
Anmol Purty | https://www.vlsisystemdesign.com/
A General Purpose Bandgap Reference IP block that generates constant voltage at output, which is...
Aloke Das
This is simple microprocessor. Instruction Set Architecture (ISA). The data bus is 16 bits wide....
Siddhant Nayak | https://www.vlsisystemdesign.com/
In this project, a vending machine with change system using Verilog HDL is proposed based on...
Sam Lim
An initial attempt to create a Test chip
Vijayan Krishnan | https://www.chipwaretechnologies.com/
The openGFX430 is a synthesizable Graphic controller written in Verilog and tailored for the...
Luca Pezzarossa
Test of new patmos
Madhuri Hemant Kadam | http://www.vlsisystemdesign.com/
CMOS OPAMP is Basic building block of analog and Mixed signal circuits. It is used in many...
Leo Moser | https://www.semify-eda.com
A generic waveform generator divided into stimulus and driver units that can be arbitrarily...
Soumil Jain | https://isn.ucsd.edu/courses/beng207/
ReRAM 16x16 array characterisation, including forming, incremental set and reset, and parallel...
Ian Zhang
Systolic Array is a classical architecture that is recently revitalized among Neural Network...
Nguyen Dao
This project demonstrates a customized Rocket Chip SoC, generated from Chipyard. The SoC is...
Dinesh Annayya
Arduino pin compatible Single RISCV 32 Bit core Project
Cra2yPierr0t | https://cpu-dev.github.io
PicoRV & Jacaranda-8 - It's a hobby heterogeneous processor!
aju narayanan | https://www.bits-pilani.ac.in/hyderabad/
a simple 16 instruction microprocessor
Abdullah YILDIZ | https://yongatek.com/
YONGA-CAN Controller is a partial implementation of CAN 2.0B standard.
Constantine Mantas
This ASIC takes as an input the header of a Blockchain and simulates the bitcoin mining process.
Po-Chun Huang | https://ece.umd.edu/
This project contains array of various sizes of 1T1R devices and a 1T1R 256x256 ReRAM module for...
Simon Waid | https://www.oeaw.ac.at/en/hephy/
This is a simple analog fronted for particle detection. The user may attach a particle detector...
Nguyen Dao
Demonstration of the open FABulous eFPGA using the OpenLane flow.
Deepak verma | https://home.iitd.ac.in/
SRAM in memory computing : The project includes SRAM In Memory Computing Accelerator.
Mathis Salmen
SoomRV is a simple superscalar Out-of-Order RISC-V microprocessor. It can execute 4 Instructions...
Allen Boston | https://github.com/lnis-uofu
User project wrapper includes the PMU version 3, SOFA 2x2 FPGA generated using OpenFPGA, and...
Dinesh Annayya
Riscduino is a Dual 32 bit RISC V based SOC design pin compatible to arduino platform and this...
Paweł Sitarz
Project instantiates HyperRAM controller for external memory chip (8MB version) connected to...
Sritam Birtia | https://www.vlsisystemdesign.com/
The main goals of this project are implementing an 8-bit bcd code counter in skywater 130nm and...
SUMANTO KAR | https://www.vlsisystemdesign.com/
This project focuses on design of a Sziklai Pair Amplifier using Google Skywater (sky130)...
Alexander Shabarshin
This is a test circuit for 3-rail async ternary selector that connects one of the 3 ternary...
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
pro_row_idct_parallel
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
Implementation of 16-bit-Han-Carlson Adder, a parallel prefix fast adder using Sky130nm PDK.
Uri Shaked | https://tinytapeout.com
Re-run of TinyTapeout 02 with an extra SkullART slot
Aman Prajapati | https://www.vlsisystemdesign.com
A Johnson counter is a modified ring counter in which the output from the last flip flop is...
Joseph Riem
GWU's project to verify gds file using efabless precheck and tapeout check.
Tejas B N | https://www.vlsisystemdesign.com/
Gray code counter is a digital counter that counts such that each successive bit patterns...
Nishad Potdar
This is an implementation of BCD to Seven Segment Decoder. The module takes 4 bit BCD input and...
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
Implementation of 16-bit-Ladner-Fischer-Adder, a parallel prefix fast adder using Sky130nm PDK.
ritesh lalwani | https://www.vlsisystemdesign.com/
The Aim of this exercise is to design a linear feedback shift register to produce a random...
Takuya Sasatani | https://www.takuyasasatani.com/
Generates multiple clocks and outputs the selected clock
Yukidamayaki
Resubmission
Janani Aravind
Radiation Hardened ALU
LOKESH MAJI | https://www.vlsisystemdesign.com/
In this project, traffic light controller on a four-way road using a sensor is proposed. A...
Himanshu Rai | https://www.vlsisystemdesign.com/
this project is about pwm generator with a feature of variable duty cycle .
Yash Kothari | https://www.vlsisystemdesign.com/
LIFO buffers are a contiguous piece of memory that require special methods to add and remove data.
Paras Vekariya
This project simulates the overlapping Moore Design for Sequence Detection where it toggles the...
Matt Venn | https://www.zerotoasiccourse.com/
Zero to ASIC course group submission for MPW8
Chithambara Moorthii J
The project includes RRAM In Memory Computing Accelerator , designed by our team at IIT...
Abdul Moiz Sheikh
The project aims to deliver a dual mode hashing accelerator which is capable of high speed...
Myrtle Shah
FABulous eFPGA fabric generated and taped out on the new gf180 process
Ruige Lee
This is the simplest version of Rift2Core. Rift2300 has no L2 cache, no L1 ICache, no L2 TLB, no...
Myrtle Shah
FPGA based on FABulous but using an experimental combined custom bitcell+tgate config routing element
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
hada_2d1_3
Abdul Moiz Sheikh
Serial peripheral interface (SPI) is one of the most widely used interfaces between...
Sahil Mahajan | www.vlsisystemdesign.com
Physical Design of a 4 bit bidirectional counter
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
Implementation of 16-bit-Kogge-Stone-Adder, a parallel prefix fast adder using Sky130nm PDK.
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
mcm_8outputs
ADITYA SINGH | https://www.vlsisystemdesign.com/
serial in parallel out shift register
Ujjawal Sharma | https://www.vlsisystemdesign.com/
A bidirectional counter is a sequential up/down That has the ability to count in both directions...
Praneeth | https://iiitdm.ac.in/
Conventional lifting based 9/7 DWT using direct implementation.
Archan Desai | https://www.vlsisystemdesign.com/
ASIC design of automatic washing machine
Jesse Cirimelli-Low | https://vlsida.soe.ucsc.edu/
This testchip includes various SRAM designs generated with OpenRAM, an open srouce memory...
Praneeth | https://iiitdm.ac.in/
32-point proposed Integer DCT using parallel architecture, odd_even_parallel_complete
Dinesh Annayya
Arduino pin compatible Single RISCV 32 Bit core Project
Praneeth | https://iiitdm.ac.in/
Conventional 13X13 proposed N-parallel (5,3) lifting based 2D DWT
Thorsten Knoll
The historic arithmetic-logic-unit (ALU) 74181 from the 70's. Pure combinatorial with 4-bit...
Alexander Shabarshin
This is a test circuit for 3-rail async ternary selector that connects one of the 3 ternary...
Staf Verhaegen
Implementation of ChipFlow example SoC with 3.3V version of the c4m-flexcell standard cells.
Xuanjia Bi | https://engineering.virginia.edu/high-performance-low-power
This is state machine that monitors water and temperature change in a closed feedback loop.
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
mcm_resource
Mehdi Saligane
TBD
Uri Shaked | https://wokwi.com
SPELL is a minimal, stack-based programming language created for The Skull CTF.
susana ortega cisneros | https://unidad.gdl.cinvestav.mx/
Another test of gf180 with a synchronous modulator for another doctoral student in electronic...
Myrtle Shah
reduced size version of the one-hot mux fabric
Tiago Silva
This project contains a digital IIR biquad filter. Adapted from:...
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
integer_mcm
Opensource FoodRev Projects
Wavelet Transform with pre-filters
Asma Mohsin | https://tinytapeout.com
Convolution Neural Network co processor is added with RISCV to enhance the performance of...
Greg Davill
An award winning serial RISCV SoC from Olof Kindgren. This project incorporates 3 separate...
Ryan Matthew Price | https://www.utep.edu/engineering/ece/
Experimental Digital Process Blocks for Incomplete PDK
Emilio Baungarte | https://unidad.gdl.cinvestav.mx/
Testing an ALU using gf180 technology, to support a recently submitted journal article titled,...
Rolf Widenfelt
16x4 bit dual port register file, with dual read ports and a single write port - perfect for the...
luis adolfo luna | https://unidad.gdl.cinvestav.mx/
Test of gf180 with an asynchronous modulator, which is part of a PhD project at Cinvestav in...
Vrushabh Damle
This is an implementation of a 4-bit carry look-ahead adder which is a fast adder. It has two...
Hari V
fastmul_32x32
Ruige Lee
This is the simplest version of Rift2Core. Rift2300 has no L2 cache, no L1 ICache, no L2 TLB, no...
Waleed Waseem
uqab is an SoC.
Praneeth | https://iiitdm.ac.in/
Conventional accumulator based 2D parallel architecture (N-outputs at a time), area and...
Uriel Jaramillo Toral | https://unidad.gdl.cinvestav.mx/
Decrypt AES 128, using skywater 130nm technology, which will serve as part of a master's thesis...
Arya Reais-Parsi | https://eecs.berkeley.edu
Stamps out BFG-generated 4-LUTs to measure their performance.
Philipp Gühring | https://libresilicon.com/
Automatically generated Test Structures with the DanubeRiver Tool, to test the Global Foundries...
Aloke Das
This is simple microprocessor. Instruction Set Architecture (ISA). The data bus is 16 bits wide....
RECEP GÜNAY
Cryptographically Secure RNG Design. (MPW6 resubmission)
Subash Polisetty
8-bit Universal Shift register that performs various operations based on a control input
Tamas Hubai
Have you played Wordle on raw silicon yet? (This is a resubmission from MPW5.)
Janani Aravind
ALU-Radiation Hardened By Design
Anish Singhani
A group submission including several small designs contributed by students at Carnegie Mellon in...
Dinesh Annayya
Riscduino Peripheral Extension Chip Set-1
Zexi Liu | https://www.cmu.edu/
This project aims to build multi-purpose characterization on-chip instruments using the...
Nishad Potdar
This is an implementation of BCD to Seven Segment Decoder. The module takes 4 bit BCD input and...
Roman Bacik
USB to UART converter
Matthew Guthaus | https://vlsida.soe.ucsc.edu/
This project contains a test chip for several OpenRAM memory configurations. The configurations...
Philipp Gühring | https://libresilicon.com/
This is a second test-design which provides several automatically generated standard cells...
Gopala Krishna Reddy Sanampudi | https://www.iiitb.ac.in/
Pulse Width Modulation is a famous technique used to create modulated electronic pulses of the...
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
Implementation of 16-bit-Sklansky-Adder, a parallel prefix fast adder using Sky130nm PDK.
Nguyen Dao
Ibex Crypto eFPGA SoC
Brown Deer Technology | www.browndeertechnology.com
This is a processor design that evolved from a tiny tapeout submission. The core implements a...
James Tandon | https://www.csueastbay.edu
A basic pulse with modulation core with 8 PWMs controled by a wishbone bus slave interface. The...
Nguyen Dao
This project demonstrates open source eFPGA generated by FABulous. This version is to support...
Harry Snell
3v3 comparator with 1v8 output. For possible future uses in ADCs. May also include other related...
Klas Nordmark
An ASIC-adapted version of the award-winning bit-serial RISC-V processo SERV, resubmitted due to...
Nguyen Dao
This submission is to test rram and its programming circuit using for eFPGA
Carl L Brando | https://umd.edu/
We have a 2x2 1T1R ReRam structure and a C4 Filter as well as some other supporting analog...
Maurya Patel | https://www.vlsisystemdesign.com/
A Traffic light controller made using sky130 technology node. Traffic lights are signaling...
Vinay Rayapati | https://www.vlsisystemdesign.com , https://www.iiitb.ac.in
This project provides an insight into the working of a few important instructions of the...
Wouter van Verre
An accelerator core for finding binary sequence with low autocorellation values
Vrushabh Damle
This is an implementation of a 4-bit carry look-ahead adder which is a fast adder. It has two...
Zeeshan Rafique | https://www.linkedin.com/company/merluit
Azadi is an SoC with a 32-bit RISC-V signal core extended version of ibex we named it "buraq",...
Debangana Mukherjee | https://www.vlsisystemdesign.com/vsd-iat/
4-bit Universal Shift Register
Joshua Stevens
A phased PWM controller for micro motor control
Marwan Abbas
SPM example user project
Sepide Asgari
Nanopore-based DNA sequencing is a unique, scalable technology, utilized to identify nucleotides...
Jure Vreča | https://github.com/jurevreca12/rvj1-caravel-soc-mpw7
A simple SoC using the custom riscv-jedro-1 processor design.
Staf Verhaegen
Test chip for higher speed IO pad cells
Jorge Angarita Pérez
A custom 5-bit multiplier
김태현 | https://github.com/thkim2031
In this chip there are four macros : 1. b-float FMA (16bit multiplication and 32bit...
Binoy B
Implementation of an 8x64 memory array
Larry Pearlstein | http://pearlstein.pages.tcnj.edu
Retarget FPGAs to standard cell.
Russell Friesenhahn
Matt Venn's famous VGA clock with SPI control
Yashwant Moses | vsdiat.com
Booth's Multiplier is based on Booth's Multiplication Algorithm. It proposes an efficient way...
Abdul Moiz Sheikh
The aim of project is to design a co-processor for floating point arithmetic and encryption...
Mehdi Saligane
Test Structures for NIST's Nanofabrication Project
Lena Hwang
A template SoC for Google sponsored Open MPW shuttles for SKY130
| https://www.vlsisystemdesign.com
A parking ticket vending machine based on FSM, implemented using verilog.
Mehdi Saligane
Test harness for MEMS sensing
Nguyen Dao
This project demonstrates an customized TinyRocket SoC, generated from Chipyard. The SoC is...
Howard Lau
This is a standalone educational RISC-V CPU, capable of running a Tetris game!
Leo Moser
A very simple SoC
priyanshu | https://www.vlsisystemdesign.com/
Shift registers are some sort of sequential logic circuitries that are majorly deployed to store...
Anirudh Sivaraman
Test project with minimal changes to caravel_user_project
Carl L Brando | https://www.umd.edu
We are planning to make a Mixed signal in-memory compute ReRAM arrray. This takeout will allow...
Deepak verma | https://home.iitd.ac.in/
SRAM in memory computing : The project includes SRAM In Memory Computing Accelerator. This is...
Luca Horn
First attempt at a Microcontroller, featuring a 4-bit CPU with re-programmable microcode....
Praneeth | https://iiitdm.ac.in/
DWT - Conventional 5/3 lifting based wavelet with 3 octaves.
Po-Chun Huang | https://ece.umd.edu/
This project contains array of various sizes 1T1R and stand-alone ReRAM test structures for...
Dinesh Annayya
This is chip is add-on to our Riscduino SCORE/DCORE/QCORE Chip set. As there are no free space...
Uriel Jaramillo Toral | https://unidad.gdl.cinvestav.mx/
This is the comparison project of the projects of the CINVESTAV GUADALAJARA community. The...
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
biquad_iir_ext
Zexi Liu | www.cmu.edu
SKYWATER Lab-on-chip IC resubmission. This project aims to build multi-purpose characterization...
Dantu Nandini Devi | https://www.vlsisystemdesign.com/
This is a model of a Freqency Divider. This model will contain a 4 bit number lines to select by...
Matt Venn
mpw7 walkthrough
Philipp Gühring | https://libresilicon.com/
This is a test-design which provides several automatically generated standard cells directly...
Zexi Liu
Lab-on-chip test IC
Jan Gray | http://fpga.org
S3GA: simple scalable serial FPGA. An area-efficient hierarchical FPGA core with serial logic...
Vladimir Milovanović | www.novelic.com
A hybride parameterizable radar signal processing accelerator
Kavya Sreedhar
Computes the Bezout coefficients associated with 1024 bit numbers with a GCD of 1.
Piotr Wegrzyn
Pipelined 16 bit cpu with custom architecture
Kenji Kise | https://www.arch.cs.titech.ac.jp/
Design a five-stage pipelining processor of RISC-V RV32I
Martin Schoeberl | https://github.com/os-chip-design/os-chip-design
The Patmos processor. A one-semester project with 12 students at the Technical University of...
Praneeth
Conventional convolution based folded DWT using Recurse 46, 32-bit Wallace tree multiplier
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
DCT4_PAR_2D
Po-Chun Huang | https://ece.umd.edu/
This project contains array of various sizes of 1T1R devices and a 1T1R 256x256 ReRAM module for...
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
iir2_direct
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
IIR-Filter-using-Baugh-Wooley-Multipler
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
dct4_par_2d
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
dct8_par_2d
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
radix2_parallel
Maximo Balestrini
Peripherals tests for future SoC targeting Micro/Circuit Python
Praneeth | https://iiitdm.ac.in/
Conventional convolution based folded DWT using Recurse 35 and 32-bit Wallace tree multiplier
Kerem Can Balı
64-Bit 2 Number - calculator
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
iir2_1multi_ext
Sameer S Durgoji | https://www.vlsisystemdesign.com/
Design of a 10 Bit Potentiometric Digital to Analog Converter with 3.3V analog voltage, 1.8V...
Tamas Hubai
Implement any combinatorial logic on 4 inputs by wiring up the pins the right way
Anish Singhani
Third iteration of open-source cryptography core implementation
Yifei Zhu | https://rioslab.org/
We come from RIOS Lab, TsingHua university, we designed a 64-bit dual-issue, out-of-order RISC-V...
YERRA BHASKARA VARA PRASAD
The smart glove transforms the hand signals to text and to speech by utilizing Arduino voice...
Furkan Ciylan
Implementation of SHA 3 Encrytion algorithm on caravel using skywater 130nm technology.
Po-Chun Huang
This project contains array of various sizes of 1T1R devices and a 1T1R 256x256 ReRAM module for...
Philipp Gühring | https://libresilicon.com/
Test Structures for Sky130 generated by DanubeRiver
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
iir6_multi_ext
Praneeth | https://www.iiitdm.ac.in/
Implementing the matrix operation of 16-point Hadamard Transform using 8-bit inputs.
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
iir6_cascade
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
iir6_direct
Talha Bin Azmat | http://isb.nu.edu.pk/rfcs2/
This project consists of a DNN accelerator which used cross bar array to perform in-memory...
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
iir6_multi_delay
Thorsten Knoll
Hardware circuit with an VGA output that displays a simple clock on the screen.
Lekan Afuye
Full ReRAM Memory banks
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
six_iir_ext
Myrtle Shah
VexRiscv+SPI flash+HyperRAM SoC built using Coriolis & PDKMaster - WIP designed to be...
MAKAM MANIKYA RAKSHITH
Serial Adder
Barak Hoffer
ReRAM block
Nicolás Orcasitas Garcia
Small digital circuit that calculates the sum of the multiples of 3 and 5 until a previously...
Sean "xobs" Cross
Wishbone PIO is an implementation of the PIO block attached to the Wishbone bus. A PIO block is...
Karthikeyan R
Nahh
Lekan Afuye
Full ReRAM Memory banks
MUKUL LOKHANDE
RISC based procesor
Jure Vreča | https://github.com/jurevreca12/
Integrates the riscv-jedro-1 processor into a very simple system-on-a-chip design.
Maher Benhouria
A simple rail-to-rail comparator with its bias circuitry to test the SKY130 analog design flow.
S Skandha Deepsita
This project is an implementation of approximate adder for error tolerant multimedia...
AASHISH TIWARY | https://www.vlsisystemdesign.com/
Arithmatic Logic Unit ALU is a processor unit which performs the task of addition, subtraction,...
Soumil Jain | https://isn.ucsd.edu/courses/beng207/
ReRAM 16x16 array characterisation, including forming, incremental set and reset, and parallel...
Mathis Salmen
SoomRV testing resubmission for MPW-8!
Rakshit Bhatia | https://www.vlsisystemdesign.com/
The universal shift register features parallel load, left-shift and right-shift serial input,...
Alexander Monakhov | https://engineering.phys.msu.ru/en/
This is a part of Uranus FPGA project. Our goal is to create open source configurable FPGA...
Subham Mohapatra | https://www.vlsisystemdesign.com/
8x PLL Clock Multiplier. Input frequency ranges from 5MHz to 12MHz and output frequency is from...
Paras Vekariya | VSD-IAT
This project simulates the overlapping Moore Design for Sequence Detection where it toggles the...
Ahmad Nofal
small summary never hurts
Tamas Hubai
Have you played Wordle on raw silicon yet?
Russell Friesenhahn | https://www.utexas.edu/
This project demonstrates a butterfly for an FFT with options to receive data from an external...
Andrew Feldman
Basic design to familiarize with this service
Raj kachhadiya | www.vlsisystemdesign.com
The information stored within these registers can be transferred with the help of shift...
Nishit Chechani | https://www.vlsisystemdesign.com/
The project below illustrates how an elevator controller can be designed for as many floors as...
Anish Singhani
CAN bus controller and teaching-oriented CPU core
Luke Leighton | http://libre-soc.org
Libre-SOC is an entirely Libre-licensed SoC based on the OpenPOWER v3.0 ISA. Layout is in...
Matthew Ballance
Quad-core RISC-V SoC with on-chip memory and peripherals
Dan Fritchman
Berkeley student-designed wireless SoC, featuring a RISC-V Rocket processor, hardware AES...
Julien OURY
Christmas tree controller (MPW5 ReRun)
Anish Singhani
ASIC implementation of the iconic Beep Boop traffic light at Carnegie Mellon University...
Muhammad Usama Zubair | https://github.com/ee-uet
Slightly modified version of UETRV_ESoC, a RISC-V based Embedded class SoC integrating 3-stage...
Nguyen Dao
Demonstration of the Fabulous FPGA design flow using the Skywater 130 process. This project...
Harald Pretl | https://iic.jku.at
We have implemented mixed signals blocks: A SAR-ADC with 12b and OSR=1...256 (decimation filter...
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
Implementation of 16-bit-Brent-Kung-Adder, a parallel prefix fast adder using Sky130nm PDK.
Aedan Cullen
`
Komal Javed | https://lampromellon.com/
Caravel_FPU integrates floating point unit with Caravel Core. It is capable of doing floating...
Anish Singhani
RISC-V SoC
Staf Verhaegen
Iteration on SRAM test vehicle that was not selected for MPW5.
Jorge Marin
Time-based capacitive sensor interface using highly-digital custom building blocks
Chithambara Moorthii J
test for precheck digital
ANCHIT PROCH
A high-performance, separately driven, noise-canceling, skew-based Voltage Controlled Ring...
Mauricio Alejandro Montanares Sepúlveda
process acoustics signals from 8 MEMS microphones with an extended frequency range up to 85 kHz...
Wenting Zhang
VerilogBoy Game Console SoC
Mufutau Akuruyejo
VSDMemSoC is a small SoC including a RISCV-based processor named RVMYTH and an external 1kB SRAM...
Myrtle Shah
Test SoC using Amaranth; Coriolis; PDKMaster for MPW4
Raj Babu
Caravel Harness based Digital Signal Controller for Embedded Control applications , the user...
RAHUL SREEKUMAR | https://engineering.virginia.edu/high-performance-low-power
The Rivest Cypher 4 is a stream cipher algorithm developed in the 1980s, remarkable for its fast...
Hari V
fastmul_16x16
Tamas Hubai
Universal logic gates, self-documenting version
Paweł Sitarz
Project instantiates HyperRAM controller for external memory chip (8MB version) connected to...
Konrad Rzeszutek Wilk
The SHA1 engine, while not the most secure nowadays is still used by git commits and TPM PCR...
Miles Segal
calculates state of cell based on state of neighbors
Iván Rodríguez Ferrández
The main goal of this project is to assess the reliability of the Global foundries 180nm...
KSHITIZ TYAGI
Testing precheck
Iván Rodríguez Ferrández | https://www.bsc.es
The main goal of this project is to assess the reliability of the SkyWater 130nm manufacturing...
Andrew Attwood | https://github.com/andrewattwood/fuserisc.git
FuseRISC will demonstrate the benefits of the tight coupling of RISC-V cores and eFPGA fabric...
Karthik Mahendra
I2C bus controller transmits 8-bit serial data to multiple targets
Mufutau Akuruyejo | httpS://WWW.vlsisystemdesign.com
VSDBabySoC is a small SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
Swarup Pulujkar | https://www.vlsisystemdesign.com
A Bandgap Reference Circuit To Generate A Constant Voltage Output That Is Insensitive To...
Ruige Lee
This is a Fake Rift2Core. There is a LFSR and Multiplier in it!
Dinesh Annayya
A arduino pin compatible RISC V Project
Staf Verhaegen
Iteration on SRAM test vehicle that failed to be selected for MPW5, MPW6 and MPW7.
Ruige Lee
There is a LFSR in it.
Julien OURY
Christmas tree controller (MPW5 ReRun)
MERL SoC-Now | https://github.com/merledu
This SoC is generated by the SoC Now Generator. It is written in Chisel.
Dinesh Annayya
Riscduino is a Dual 32 bit RISC V based SOC design pin compatible to arduino platform and this...
RAVI KIRAN REDDY GOGIREDDY | https://www.iiitb.ac.in/. https://www.vlsisystemdesign.com/
detecting the sequence 10111.
Bhawandeep Singh
The project is a realization of darkriscv processor using openlane and skywater pdk. It has a...
Giter CN
folk of riscduino_qcore for test
Philipp Gühring | https://libresilicon.com/
At Libresilicon we have been working for several years on making chipdesign and production...
Dinesh Annayya
Arduino pin compatible Single RISCV 32 Bit core Project
Egor Lukyanchenko
Uranus eFPGA with nonvolatile config in eFuse array.
Ruige Lee
This is an almost full-functional version of Rift2Core. Rift2330 has the smallest L2 cache, L1...
Paweł Sitarz
Project instantiates HyperRAM driver for external memory chip (8MB version) and additional...
Christoph Weiser
This is a Analog to Digital Converter based on the popular SAR architecture. It has 8-bit...
Christoph Weiser
This submission consists of a updated 8-bit SAR-ADC, basic analog support circuitry, such as...
Giray Pultar
Key value store implemented on asic.
Merl Uit
This submission is for Ibtida-I which was selected for the First MPW Shuttle. Due to the issues...
M. Shalan | http://efabless.com
Caravel management SoC attached to the largest possible SRAM that can fit the user's area.
Janani Aravind | https://www.ncat.edu/
This is a digital 4-bit ALU_XOR design.
Iván Rodríguez Ferrández
This design is a radiation tolerant UART server that can be used for low level control of...
James Stine | https://vlsiarch.ecen.okstate.edu/
Caravel_RISCV_OSU is an implementation of a single-cycle RISC-V processor inside of the Caravel...
Matthew Ballance | http://github.com/mballance
A simple RISC-V core+peripherals subsystem for the Google-sponsored Open MPW shuttles for SKY130.
Siva Prasad
A attempt to integrate various peripherals like I2C, I2S, UART, SPI, QSPI , JTAG, PWM, GPIO ,...
Siva Prasad
A gpio expander for the caravel harness to realize a small microcontroller
Hongzhe Jiang
This project is intended to implement a closed-loop class-d audio amplifier with 1.8 V power...
Thinh Pham
A SoC with two crypto-supported RISC-V cores.
Uzair Ahmad | http://isb.nu.edu.pk/rfcs2/
Space application Integrated Circuits (ICs) are prone to radiation particles, which are present...
Adithya Sunil Edakkadan
2.87 GHz frequency synthesizer with programmable sweep.
Rana Muhammad Shahid Jamil | http://isb.nu.edu.pk/rfcs2/
This project implements an approximate multiplier for image processing applications
Wajeh
This Is A Machine-Mode (M-Mode) Only, 32-Bit Cpu Small Core Which Supports Risc-V’s Integer (I),...
Harald Pretl
As a classroom project at Johannes Kepler University, we are designing a delta-sigma audio DAC,...
Rameen Anwar | https://github.com/merledu
This project is the extended version of Azadi-SoC, which includes all of the peripherals which...
Javier Contreras
Test structures for the study of ionizing radiation tolerance in the Skywater 130 process.
ROHINTH RAM R.V. | https://www.vlsisystemdesign.com/
Two Stage CMOS Operational Amplifier
Omar Mohamed Saadawy
Voltmeter & Ammeter
