The proposed circuit is a Digitally Programmable Gain Amplifier (DPGA) designed to amplify voltage signals with programmable gain options ranging from 1 V/V to 256 V/V. The main core is an OTA (Operational Transconductance Amplifier) Miller with an output buffer configured as an inverter amplifier. The key feature of the circuit is its programmable gain, which is achieved by controlling the feedback resistances through 8 CMOS switches (Transmission Gates). These switches are configured based on a binary word stored in a shift register, which can be controlled externally through a Serial Peripheral Interface (SPI). The DPGA is intended to operate with a 1.8 V power supply and has a unity gain frequency of 5 MHz. The circuit's performance specifications include a minimum open-loop gain of 60 dB, a gain bandwidth product (GBW) of 5 MHz, a phase margin of at least 60 degrees, a slew rate of 0.8 V/µs, and a Common-Mode Rejection Ratio (CMRR) greater than 80 dB. Expected Outcome:* The expected outcome of this DPGA design is to achieve a digitally controllable amplifier with a wide range of programmable gains, allowing for flexibility in different applications. The circuit should exhibit a high CMRR, ensuring effective rejection of common-mode signals, and provide a relatively large open-loop gain to maintain accurate amplification across the gain range. With a GBW of 5 MHz and a phase margin of at least 60 degrees, the amplifier will maintain stable performance across various frequency ranges. The use of the SPI interface will allow for easy control and integration with external devices.