SHA256 BASED MINER

The project presents an implementation of Custom Miner on open-source ASIC implementation. Cryptocurrency mining generates new units and validates transactions through complex problem-solving. Miners compete, and the first successful one adds a new block to the blockchain, earning new coins. "256-bit" refers to the length of the cryptographic hash function, e.g., SHA-256, ensuring security. A "256Bit coin miner" likely denotes specialized hardware like an ASIC for SHA-256.

Developing an ASIC involves understanding SHA-256, RISC-V architecture, using Verilog for design, implementing SHA-256 hardware acceleration, integrating C program execution on RISC-V, optimizing performance, testing and simulation, semiconductor manufacturing, addressing power and cooling concerns. Apart from that this design also have capability to test Cryptographic algorithms due to built-in Riscv Core. Build-in Custom wishbone to uart core for high speed transfer of data from SHA256 to GPIO.

Final Version.