KWS inference on chip

This document is a simple outline for our RISC-V based KWS accelerator.
Fixed-point arithmetic is adopted as a trade-off between project size and inference performance. Quantisation from 32 bits floating-point to 4 bits fixed-points is further used to adapt the project size. All buffers are connected through wishbone bus to Caravel SRAM. The input features and weights are initialized to the Caravel RAM by the RISC-V CPU.

To save chip area and cost, we will adopt a small-scale MAC array and small-capacity on-chip buffers for CNN computation The major components include
1. A finite state machine as a controller for fetching instructions and orchestrating other modules
2. A filterbank for feature extraction
(CNN component below)
3.Nomalisation pool
4.Seperate buffers for caching input features, weights, and output features,
5.A Matrix module to flatten and rearrange the input features into feature matrices compatible with the MAC array
6.A multiply-and-accumulate (MAC) array is adopted to compute matrix multiplications.
7.A Add unit (array)for element-wise sum layers
8.A Mutiply unit (array)for element-wise product layers
9.A Sumlayer unit for calculating sum in fully-connected layers
10.A ReLU Activation Unit is implemented with a comparator
11.A Sigmoid Activation Unit via piecewise linear or lookup table approach
12.Weight FIFOs for matrix data flow during computing matrix multiplications.

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