Riscduino Peripheral Extension-1 SOC


Permission to use, copy, modify, and/or distribute this soc for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.

THE SOC IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOC INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOC.

• Overview
• Block Diagram
• Key Feature

This is chip is add-on to our Riscduino SCORE/DCORE/QCORE Chip set. As there are no free space in the previous chip and this chip will be host additional function like mac core, stepper motor and new feature as needed. This project uses only open source tool set for simulation,synthesis and backend tools. The SOC flow follow the openlane methodology and SOC environment is compatible with efabless/carvel methodology.

    * Open sourced under Apache-2.0 License (see LICENSE file) - unrestricted commercial use allowed.
    * 100MB/10MB MAC core
    * 4 pin Stepper Motor controller
    * 8 x 2KB SRAM with MBIST controller
    * Open-source tool set
       * simulation - iverilog
       * synthesis  - yosys
       * backend/sta - openlane tool set
    * Verification suite provided.

The simulation package includes the following tests:

• 1.user_uart_master - Standalone uart master test
• 2.user_mac_test1 - Standalone mac test
• 3.user_mbist_test1 - Standalone mbist test1
• 4.user_mbist_test2 - Standalone mbist test2

• 1.wb_port - Complete caravel User Wishbone validation
• 2.uart_master_test1 - uart master test1 with caravel
• 3.uart_master_test2 - uart master test2 with caravel

#Timing Analysis

   make setup-timing-scripts
   make install
   make install_mcw

his will update Caravel design files and install the scripts for running timing.

make extract-parasitics
make create-spef-mapping
make caravel-sta

#Other Miscellaneous Targets The makefile provides a number of useful that targets that can run LVS, DRC, and XOR checks on your hardened design outside of openlane’s flow.

Run make help to display available targets.

Run lvs on the mag view,

make lvs-<macro_name>

Run lvs on the gds,

make lvs-gds-<macro_name>

Run lvs on the maglef,

make lvs-maglef-<macro_name>

Run drc using magic,

make drc-<macro_name>

Run antenna check using magic,

make antenna-<macro_name>

Run XOR check,

make xor-wrapper

Riscduino Soc flow uses Openlane tool sets.

1. Synthesis
   1. yosys - Performs RTL synthesis
   2. abc - Performs technology mapping
   3. OpenSTA - Pefroms static timing analysis on the resulting netlist to generate timing reports
2. Floorplan and PDN
   1. init_fp - Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing)
   2. ioplacer - Places the macro input and output ports
   3. pdn - Generates the power distribution network
   4. tapcell - Inserts welltap and decap cells in the floorplan
3. Placement
   1. RePLace - Performs global placement
   2. Resizer - Performs optional optimizations on the design
   3. OpenPhySyn - Performs timing optimizations on the design
   4. OpenDP - Perfroms detailed placement to legalize the globally placed components
4. CTS
   1. TritonCTS - Synthesizes the clock distribution network (the clock tree)
5. Routing
   1. FastRoute - Performs global routing to generate a guide file for the detailed router
   2. CU-GR - Another option for performing global routing.
   3. TritonRoute - Performs detailed routing
   4. SPEF-Extractor - Performs SPEF extraction
6. GDSII Generation
   1. Magic - Streams out the final GDSII layout file from the routed def
   2. Klayout - Streams out the final GDSII layout file from the routed def as a back-up
7. Checks
   1. Magic - Performs DRC Checks & Antenna Checks
   2. Klayout - Performs DRC Checks
   3. Netgen - Performs LVS Checks
   4. CVC - Performs Circuit Validity Checks

• turbo8051 https://opencores.org/projects/turbo8051
• Julien OURY MPW Project https://github.com/JulienOury/ChristmasTreeController.git
• opengfx430 https://github.com/olgirard/opengfx430
• openMSP430 https://opencores.org/websvn/filedetails?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fdoc%2FopenMSP430.pdf
• slau049f https://www.ti.com/lit/ug/slau049f/slau049f.pdf
• LT24 Card http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=68&No=892&PartNo=2#heading