YiFive SOC Integrated Syntacore SCR1 Open-source RISC-V compatible MCU-class core + 8 bit SDRAM Memory Controller + Quad SPI. Both Risc V and SDRAM controller are silicon-proven IP.

Key feature

• Open sourced under Apache-2.0 License (see LICENSE file) - unrestricted commercial use allowed.
• industry-grade and silicon-proven Open-Source RISC-V core from syntacore
• industry-graded and silicon-proven 8-bit SDRAM controller
• Quad SPI Master
• I2C Master
• UART 16Byte FIFo
• Wishbone compatible design
• Written in System Verilog
• Open-source tool set
• simulation - iverilog
• synthesis - yosys
• backend/sta - openlane tool set
• Verification suite provided.

Sub IP features

RISC V Core

YiFive SOC Integrated Syntacore SCR1 Open-source RISV-V compatible MCU-class core. It is industry-grade and silicon-proven IP. Git link: https://github.com/syntacore/scr1

RISC V Core Key feature

• RV32I or RV32E ISA base + optional RVM and RVC standard extensions
• Machine privilege mode only
• 2 to 4 stage pipeline
• Optional Integrated Programmable Interrupt Controller with 16 IRQ lines
• Optional RISC-V Debug subsystem with JTAG interfaceOptional on-chip Tightly-Coupled Memory

8bit SDRAM Controller

Due to number of pin limitation in carvel shuttle, YiFive SOC integrate 8bit SDRAM controller. This is a silicon proven IP. IP Link: https://opencores.org/projects/sdr_ctrl

SDRAM Controller key Feature

• 8/16/32 Configurable SDRAM data width
• Wish Bone compatible
• Application clock and SDRAM clock can be async
• Programmable column address
• Support for industry-standard SDRAM devices and modules
• Supports all standard SDRAM functions.
• Fully Synchronous; All signals registered on positive edge of system clock.
• One chip-select signals
• Support SDRAM with four banks
• Programmable CAS latency
• Data mask signals for partial write operations
• Bank management architecture, which minimizes latency.
• Automatic controlled refresh