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MPW-6 Shuttle Projects

8 bit Priority Encoder public


It Encode data Our priority vice

synth_test public

Benoit Callebaut

Nest generation audio synthetizer engine

ButtiChip01 public

ぶっちー ゆっくり | https://www.himasugirubutti.com


mips32_processor public

aju narayanan | https://www.bits-pilani.ac.in/hyderabad/

a simple 16 instruction microprocessor

Riscduino-SCore(S3) public

Dinesh Annayya

Arduino pin compatible Single RISCV 32 Bit core Project

Asicle rollover public

Tamas Hubai

Have you played Wordle on raw silicon yet? (This is a resubmission from MPW5.)

TinyRocket_SoC public

Nguyen Dao

This project demonstrates an customized TinyRocket SoC, generated from Chipyard. The SoC is...

YatCPU public

Howard Lau

This is a standalone educational RISC-V CPU, capable of running a Tetris game!

ReRAM Devices... public

Po-Chun Huang | https://ece.umd.edu/

This project contains array of various sizes 1T1R and stand-alone ReRAM test structures for...

Reram array-MPW6 public

Lekan Afuye

Full ReRAM Memory banks

ReRAM-block public

Barak Hoffer

ReRAM block

rvj1-caravel-soc public

Jure Vreča | https://github.com/jurevreca12/

Integrates the riscv-jedro-1 processor into a very simple system-on-a-chip design.

ORDER_PRGA_MPW6_v2 public

Ang Li

A 512-LUT4 FPGA generated using PRGA (Princeton Reconfigurable Gate Array); An 8x8 array of...

SRAMTestVehicleSequel public

Staf Verhaegen

Iteration on SRAM test vehicle that was not selected for MPW5.

riscduino_qcore_folk public

Giter CN

folk of riscduino_qcore for test

Four-Bit-ALU_XOR---MPW-6 public

Janani Aravind | https://www.ncat.edu/

This is a digital 4-bit ALU_XOR design.

Patently-Obvious-ASIC public

Yukidamayaki | analogmiko.com

This project is an RTL-level clone of the HP35 calculator (CTC, ARC & ROM), based on RJW's prior...

HyperRAM Interface public


Resubmission of Steve Goldsmith's project.

Adaptive... public

Lê Đức Hùng | http://www.hcmus.edu.vn

We make implementation of a flexible 32-point Discrete Cosine Transform (DCT). The architecture...

CMOS cascode... public

Krishna Kummarapalli

This is a high speed dynamic comparator

Experiar-SoC public

Charlie Smith

Experiar SoC is a dual RV32I core processor with peripherals including PWM, SPI, UART, and VGA.

Patmos Real-Time... public

Martin Schoeberl | https://github.com/os-chip-design/os-chip-design

A time-predictable processor called Patmos. This was a 13-week project by 12 students at the...

Riscduino-QCore... public

Hanming Wang

Riscduino-QCore Clone

REST_II public

Sajjad Ahmed | https://github.com/merledu

REST(Resource efficient SRAM based TCAM) is test project for exprimenting the SRAM based TCAMs in ASIC.

Mixed_signal_circuits_v2 public

Carl L Brando | https://www.umd.edu

Mixed signal circuits for analog synapses.

SEL_SET public

Janani Aravind

Four-bit ALU that is hardened to mitigate Single-Event Latch-ups and Transients

Cryptographically... public


Cryptographically Secure RNG Slave. Integrates AES cipher and double scroll chaotic RNG circuit...

Floating_Point_Un... public

MERL_DSU | https://merledupk.org/

This is the first ever Bfloat16 precision floating point unit designed by undergraduate students...

my_caravel_analog_project public

Riku Anan

This is my first project. 6-bit saradc.

Floating_Point_Un... public

MERL_DSU | https://merledupk.org/

This is the Floating point unit which supports the IEEE-754 Half Precision format. This FPU is...

Analog Frontend... public

Simon Waid

This is a simple analog fronted for particle detection. The user may attach a particle detector...

FT8 Receiver Test public

Ryan Wans | https://www.radiostack.com/

A sample tapeout to test needed circuitry for a fully-functional FT8 transceiver.

HSV Mixer public

Johan Euphrosine (proppy) | https://www.google.com/

HSV to RGB color convertor using XLS.

Analog Chaotic Oscillator public

Parker Hardy | http://bemosc.olemiss.edu/

This is a chaotic oscillator with three-transistor based nonlinear map circuit.

Leaf public

Daniel Santos

a small 32-bit RISC-V core for IoT applications.

Ibex Implementation public

Ming Hung Chen

Ibex implementation for pulpino design

Patmos public

Martin Schoeberl | https://github.com/os-chip-design/os-chip-design

The Patmos processor. A one-semester project with 12 students at the Technical University of...

digital biquad filter public

Tiago Silva

This project contains a 16bit digital biquad filter.

Bitcoin Mining Asic... public

Constantine Mantas

This ASIC takes as an input the header of a Blockchain and outputs a valid 256bit hashed output...

1T1R RRAM... public

Chithambara Moorthii J | https://home.iitd.ac.in/

The project includes 1T1R RRAM crossbar array with peripherals, by researchers mentioned below...

SoC_Now public

Usman Zain Ul Abedin | https://github.com/merledu

This SoC is generated by the SoC Now Generator which is the final year project of undergraduate...

Natalius_SoC public

Fabio Andres Guzman Figueroa

Natalius is a compact, capable and fully embedded 8 bit RISC processor core described 100% in...

Figaro Oscillator public

Kaya Demir

Ring oscillator and figaro

Microwatt MPW6 public

Anton Blanchard

Microwatt is a 64 bit OpenPOWER core written in VHDL. It includes an IEEE 754 double-precision...

SAPA-01 public

Le Duc Anh

This is SAPA-01 project.

Hack SoC - MPW-6 public

Maximo Balestrini

Hardware implementation of the Hack Computer from the Nand to Tetris courses

Ghazi_DFT public

Nimra Khan

DFT of ghazi Soc

FPGA Programming... public

Allen Boston | https://github.com/lnis-uofu

The Programming Management Unit will serve as a macro that can be placed near a FPGA to handle...

Motius Pong public


The first game: PONG

Optimised-Strong-... public

Ria Rashid

This is the design of an optimised Strong ARM Latch using modified particle swarm optimisation.

Hyperspace public

Vladimir Milovanović | www.novelic.com

A hybride parameterizable radar signal processing accelerator

Riscduino-QCore (Q1) public

Dinesh Annayya

Riscduino is a Quad 32 bit RISC V based SOC design pin compatible to arduino platform and this...

TopmetalSe-A-Low-... public

Xiaochen Ni | https://www.npl.washington.edu/

The TopmetalSe is a pixelated charge sensor in the Skywater 130nm process, designed for the...

ISA 16 bit Microprocessor public

Aloke Das

This is simple microprocessor. Instruction Set Architecture (ISA). The data bus is 16 bit wide....

Free and open... public

Hanssel Morales

Hardware accelerator that implements standard encryption algorithm AES ECB.

Chip_pp public

Hiroshi Heinai

Original IC project

Riscduino-DCore (D1) public

Dinesh Annayya

Riscduino is a Dual 32 bit RISC V based SOC design pin compatible to arudino platform and this...

Zero to ASIC... public

Matt Venn | https://zerotoasiccourse.com

Zero to ASIC course group submission MPW6

OpenRAM Test Design public

Serdar Ünal | https://tutel.bilgem.tubitak.gov.tr/

This project was designed to be able to test the SRAM macros generated using OpenRAM flow.

Mixed_signal_circ... public

Carl L Brando | https://www.umd.edu

Basic ReRAM, Floating Gate, and other analog structures.

CMOS High Speed... public

Krishna Kummarapalli

This is a novel dynamic comparator design that improves the common mode performance. Its...


Shumpei Kawasaki | https://swhwc.com

Targeting 5-year continuous operation, a solar panel, a power supply board, a logic board, and...

caravel_iee2433 public

Agustín Campeny

OP-AMP design as final project for analog integrated circuits design course

Tensor... public

Yinghao Ren | The University of Tokyo

Using NNgen to generate circuits


Onur Karataş

In this study, a digital RNG based on chaotic oscillators was implemented using the SKY130 process node.

Efabless_MPW6_riscduino public

Halil ibrahim Kaysici

This is a clone project from dineshannayya/riscduino

My CPU - A subleq ISA... public

pon dahai

I build a subleq CPU on the breadboard and I want make it become a IC.

MPW_TEST public

Bo Feng

A test project for the open MPW shuttle.

seven segment seconds public

Matt Venn

walkthrough tutorial for Efabless

demo_project public

Divyam Pandya

Testing the features of efabless


Georgios Tziantzioulis

A 512-LUT4 FPGA generated using PRGA (Princeton Reconfigurable Gate Array); An 8x8 array of...

toysram public

Bill Flynn | https://openpower.foundation/

This is a test site for a custom array design.

SonaronChip8 public

Mauricio Alejandro Montanares Sepúlveda

process acoustics signals from 8 MEMS microphones with an extended frequency range up to 85 kHz...

10b ADC and... public

Christoph Weiser

This submission features: 10b SAR-ADC, Bandgap reference, Testbuffer, Clock generator, LDO,...

ChristmasTreeCont... public

Julien OURY

Christmas tree controller (MPW5 ReRun)

4 x PWM public

Serdar Ünal | https://tutel.bilgem.tubitak.gov.tr/

PWM (Pulse Width Modulation) modules (resubmission from MPW-5)

Miranda FPGA MPW6 public

Alexander Monakhov

Next step of Uranus FPGA project with sophisticated LUT, BRAM, tile architecture.

RhythmIC (old) public

Abhinav Uppal | https://isn.ucsd.edu/courses/beng207/

FOSSi cochlea implementing a wavelet filter bank in sky130.

test public

הוד טויטו


Goosey Autonomous VR public

Ozgur | https://goosey.org

Thanks to this autonomous VR software and hardware, so its planned that peoples will make their...

Azadi_DFT public

Rameen Anwar | https://github.com/merledu

This project is the extended version of Azadi-SoC, which includes all of the peripherals which...

Temporal Runtime... public

Ruediger Ehlers

This is a specialized on-chip microcontroller/SoC component for performing runtime monitoring of...

Floating_Point_Un... public

MERL_DSU | https://merledupk.org/

This is the first ever Single Precision Floating Point Unit designed by Undergraduate Students...

YONGA-Modbus Controller public

Burak Yakup Çakar | https://yongatek.com/

A Modbus controller which has a read(03h) and a write(10h) function. The controller provides...

RamenIC public


This is a timer IC to help us make Ramen.