Siddharth
It Encode data Our priority vice
Benoit Callebaut
Nest generation audio synthetizer engine
aju narayanan | https://www.bits-pilani.ac.in/hyderabad/
a simple 16 instruction microprocessor
Dinesh Annayya
Arduino pin compatible Single RISCV 32 Bit core Project
Tamas Hubai
Have you played Wordle on raw silicon yet? (This is a resubmission from MPW5.)
Nguyen Dao
This project demonstrates an customized TinyRocket SoC, generated from Chipyard. The SoC is...
Howard Lau
This is a standalone educational RISC-V CPU, capable of running a Tetris game!
Po-Chun Huang | https://ece.umd.edu/
This project contains array of various sizes 1T1R and stand-alone ReRAM test structures for...
Lekan Afuye
Full ReRAM Memory banks
Barak Hoffer
ReRAM block
Jure Vreča | https://github.com/jurevreca12/
Integrates the riscv-jedro-1 processor into a very simple system-on-a-chip design.
Ang Li
A 512-LUT4 FPGA generated using PRGA (Princeton Reconfigurable Gate Array); An 8x8 array of...
Staf Verhaegen
Iteration on SRAM test vehicle that was not selected for MPW5.
Giter CN
folk of riscduino_qcore for test
Janani Aravind | https://www.ncat.edu/
This is a digital 4-bit ALU_XOR design.
Yukidamayaki | analogmiko.com
This project is an RTL-level clone of the HP35 calculator (CTC, ARC & ROM), based on RJW's prior...
RECEP GÜNAY
Resubmission of Steve Goldsmith's project.
Lê Đức Hùng | http://www.hcmus.edu.vn
We make implementation of a flexible 32-point Discrete Cosine Transform (DCT). The architecture...
Krishna Kummarapalli
This is a high speed dynamic comparator
Charlie Smith
Experiar SoC is a dual RV32I core processor with peripherals including PWM, SPI, UART, and VGA.
Martin Schoeberl | https://github.com/os-chip-design/os-chip-design
A time-predictable processor called Patmos. This was a 13-week project by 12 students at the...
Hanming Wang
Riscduino-QCore Clone
Sajjad Ahmed | https://github.com/merledu
REST(Resource efficient SRAM based TCAM) is test project for exprimenting the SRAM based TCAMs in ASIC.
Carl L Brando | https://www.umd.edu
Mixed signal circuits for analog synapses.
Janani Aravind
Four-bit ALU that is hardened to mitigate Single-Event Latch-ups and Transients
RECEP GÜNAY
Cryptographically Secure RNG Slave. Integrates AES cipher and double scroll chaotic RNG circuit...
MERL_DSU | https://merledupk.org/
This is the first ever Bfloat16 precision floating point unit designed by undergraduate students...
Riku Anan
This is my first project. 6-bit saradc.
MERL_DSU | https://merledupk.org/
This is the Floating point unit which supports the IEEE-754 Half Precision format. This FPU is...
Simon Waid
This is a simple analog fronted for particle detection. The user may attach a particle detector...
Ryan Wans | https://www.radiostack.com/
A sample tapeout to test needed circuitry for a fully-functional FT8 transceiver.
Johan Euphrosine (proppy) | https://www.google.com/
HSV to RGB color convertor using XLS.
Parker Hardy | http://bemosc.olemiss.edu/
This is a chaotic oscillator with three-transistor based nonlinear map circuit.
Daniel Santos
a small 32-bit RISC-V core for IoT applications.
Ming Hung Chen
Ibex implementation for pulpino design
Martin Schoeberl | https://github.com/os-chip-design/os-chip-design
The Patmos processor. A one-semester project with 12 students at the Technical University of...
Tiago Silva
This project contains a 16bit digital biquad filter.
Constantine Mantas
This ASIC takes as an input the header of a Blockchain and outputs a valid 256bit hashed output...
Chithambara Moorthii J | https://home.iitd.ac.in/
The project includes 1T1R RRAM crossbar array with peripherals, by researchers mentioned below...
Usman Zain Ul Abedin | https://github.com/merledu
This SoC is generated by the SoC Now Generator which is the final year project of undergraduate...
Fabio Andres Guzman Figueroa
Natalius is a compact, capable and fully embedded 8 bit RISC processor core described 100% in...
Kaya Demir
Ring oscillator and figaro
Anton Blanchard
Microwatt is a 64 bit OpenPOWER core written in VHDL. It includes an IEEE 754 double-precision...
Le Duc Anh
This is SAPA-01 project.
Maximo Balestrini
Hardware implementation of the Hack Computer from the Nand to Tetris courses
Nimra Khan
DFT of ghazi Soc
Allen Boston | https://github.com/lnis-uofu
The Programming Management Unit will serve as a macro that can be placed near a FPGA to handle...
Kev
The first game: PONG
Ria Rashid
This is the design of an optimised Strong ARM Latch using modified particle swarm optimisation.
Vladimir Milovanović | www.novelic.com
A hybride parameterizable radar signal processing accelerator
Dinesh Annayya
Riscduino is a Quad 32 bit RISC V based SOC design pin compatible to arduino platform and this...
Xiaochen Ni | https://www.npl.washington.edu/
The TopmetalSe is a pixelated charge sensor in the Skywater 130nm process, designed for the...
Aloke Das
This is simple microprocessor. Instruction Set Architecture (ISA). The data bus is 16 bit wide....
Hanssel Morales
Hardware accelerator that implements standard encryption algorithm AES ECB.
Hiroshi Heinai
Original IC project
Dinesh Annayya
Riscduino is a Dual 32 bit RISC V based SOC design pin compatible to arudino platform and this...
Matt Venn | https://zerotoasiccourse.com
Zero to ASIC course group submission MPW6
Serdar Ünal | https://tutel.bilgem.tubitak.gov.tr/
This project was designed to be able to test the SRAM macros generated using OpenRAM flow.
Carl L Brando | https://www.umd.edu
Basic ReRAM, Floating Gate, and other analog structures.
Krishna Kummarapalli
This is a novel dynamic comparator design that improves the common mode performance. Its...
Shumpei Kawasaki | https://swhwc.com
Targeting 5-year continuous operation, a solar panel, a power supply board, a logic board, and...
Agustín Campeny
OP-AMP design as final project for analog integrated circuits design course
Onur Karataş
In this study, a digital RNG based on chaotic oscillators was implemented using the SKY130 process node.
Halil ibrahim Kaysici
This is a clone project from dineshannayya/riscduino
pon dahai
I build a subleq CPU on the breadboard and I want make it become a IC.
Bo Feng
A test project for the open MPW shuttle.
Matt Venn
walkthrough tutorial for Efabless
Divyam Pandya
Testing the features of efabless
Georgios Tziantzioulis
A 512-LUT4 FPGA generated using PRGA (Princeton Reconfigurable Gate Array); An 8x8 array of...
Bill Flynn | https://openpower.foundation/
This is a test site for a custom array design.
Mauricio Alejandro Montanares Sepúlveda
process acoustics signals from 8 MEMS microphones with an extended frequency range up to 85 kHz...
Christoph Weiser
This submission features: 10b SAR-ADC, Bandgap reference, Testbuffer, Clock generator, LDO,...
Julien OURY
Christmas tree controller (MPW5 ReRun)
Serdar Ünal | https://tutel.bilgem.tubitak.gov.tr/
PWM (Pulse Width Modulation) modules (resubmission from MPW-5)
Alexander Monakhov
Next step of Uranus FPGA project with sophisticated LUT, BRAM, tile architecture.
Abhinav Uppal | https://isn.ucsd.edu/courses/beng207/
FOSSi cochlea implementing a wavelet filter bank in sky130.
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Ozgur | https://goosey.org
Thanks to this autonomous VR software and hardware, so its planned that peoples will make their...
Rameen Anwar | https://github.com/merledu
This project is the extended version of Azadi-SoC, which includes all of the peripherals which...
Ruediger Ehlers
This is a specialized on-chip microcontroller/SoC component for performing runtime monitoring of...
MERL_DSU | https://merledupk.org/
This is the first ever Single Precision Floating Point Unit designed by Undergraduate Students...
Burak Yakup Çakar | https://yongatek.com/
A Modbus controller which has a read(03h) and a write(10h) function. The controller provides...
Tako
This is a timer IC to help us make Ramen.