Riscduino is a Dual 32 bit RISC V based SOC design pin compatible to arudino platform and this soc targetted for efabless Shuttle program. This project uses only open source tool set for simulation,synthesis and backend tools. The SOC flow follow the openlane methodology and SOC environment is compatible with efabless/carvel methodology.
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* Open sourced under Apache-2.0 License (see LICENSE file) - unrestricted commercial use allowed.
* Dual 32 Bit RISC-V core
* 2KB SRAM for instruction cache
* 2KB SRAM for data cache
* 2KB SRAM for Tightly coupled memory - For Data Memory
* Quad SPI Master with 4 Chip select, supports both SPI flash and SRAM interface
* 2 x UART with 16Byte FIFO
* USB 1.1 Host
* I2C Master
* UART Master
* Simple SPI Master with 4 Chip select
* 6 Channel ADC (in Progress)
* 6 x PWM
* 3 x Timer (16 Bit), 1us/1ms/1second resolution
* Pin Compatbible to arudino uno
* Wishbone compatible design
* Written in System Verilog
* Open-source tool set
* simulation - iverilog
* synthesis - yosys
* backend/sta - openlane tool set
* Verification suite provided.
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| MPW | Tape-out | Project Name | Project Details | Github | Efabless |
| MPW-2 | 18-June-2021 | YiFive | Single 32bit RISCV core without cache + SDRAM Controller + WB Interconnect | Link | Link |
| MPW-3 | 15-Nov-2021 | Riscduino | Single 32bit RISCV core without cache + Onchip SRAM + WB Interconnect | Link | Link |
| MPW-4 | 31-Dec-2021 | Riscduino-R1 | Single 32bit RISCV core with cache + Onchip SRAM + WB Inter Connect | Link | Link |
| MPW-5 | 21-Mar-2022 | Riscduino-SCORE | Single 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar | Link | Link |
| MPW-5 | 21-Mar-2022 | Riscduino-DCORE | Dual 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar | Link | Link |
| MPW-5 | 21-Mar-2022 | Riscduino-QCORE | Quad 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar | Link | Link |
Carvel SOC provides 38 GPIO pins for user functionality. Riscduino SOC GPIO Pin Mapping as follows vs ATMEGA328 and Arudino
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| ATMGA328 Pin No | Functionality | Arudino Pin Name | Carvel Pin Mapping |
| Pin-1 | PC6/RESET | digital_io[0] | |
| Pin-2 | PD0/RXD[0] | D0 | digital_io[1] |
| Pin-3 | PD1/TXD[0] | D1 | digital_io[2] |
| Pin-4 | PD2/RXD[1]/INT0 | D2 | digital_io[3] |
| Pin-5 | PD3/INT1/OC2B(PWM0) | D3 | digital_io[4] |
| Pin-6 | PD4/TXD[1] | D4 | digital_io[5] |
| Pin-7 | VCC | - | |
| Pin-8 | GND | - | |
| Pin-9 | PB6/XTAL1/TOSC1 | digital_io[6] | |
| Pin-10 | PB7/XTAL2/TOSC2 | digital_io[7] | |
| Pin-11 | PD5/SS[3]/OC0B(PWM1)/T1 | D5 | digital_io[8] |
| Pin-12 | PD6/SS[2]/OC0A(PWM2)/AIN0 | D6 | digital_io[9] /analog_io[2] |
| Pin-13 | PD7/A1N1 | D7 | digital_io[10]/analog_io[3] |
| Pin-14 | PB0/CLKO/ICP1 | D8 | digital_io[11] |
| Pin-15 | PB1/SS[1]OC1A(PWM3) | D9 | digital_io[12] |
| Pin-16 | PB2/SS[0]/OC1B(PWM4) | D10 | digital_io[13] |
| Pin-17 | PB3/MOSI/OC2A(PWM5) | D11 | digital_io[14] |
| Pin-18 | PB4/MISO | D12 | digital_io[15] |
| Pin-19 | PB5/SCK | D13 | digital_io[16] |
| Pin-20 | AVCC | - | |
| Pin-21 | AREF | analog_io[10] | |
| Pin-22 | GND | - | |
| Pin-23 | PC0/ADC0 | A0 | digital_io[18]/analog_io[11] |
| Pin-24 | PC1/ADC1 | A1 | digital_io[19]/analog_io[12] |
| Pin-25 | PC2/ADC2 | A2 | digital_io[20]/analog_io[13] |
| Pin-26 | PC3/ADC3 | A3 | digital_io[21]/analog_io[14] |
| Pin-27 | PC4/ADC4/SDA | A4 | digital_io[22]/analog_io[15] |
| Pin-28 | PC5/ADC5/SCL | A5 | digital_io[23]/analog_io[16] |
| Additional Pad used for Externam ROM/RAM/USB | |||
| Sflash | sflash_sck | digital_io[24] | |
| SFlash | sflash_ss0 | digital_io[25] | |
| SFlash | sflash_ss1 | digital_io[26] | |
| SFlash | sflash_ss2 | digital_io[27] | |
| SFlash | sflash_ss3 | digital_io[28] | |
| SFlash | sflash_io0 | digital_io[29] | |
| SFlash | sflash_io1 | digital_io[30] | |
| SFlash | sflash_io2 | digital_io[31] | |
| SFlash | sflash_io3 | digital_io[32] | |
| SSRAM | Reserved | digital_io[33] | |
| SSRAM | uartm rxd | digital_io[34] | |
| SSRAM | uartm txd | digital_io[35] | |
| usb1.1 | usb_dp | digital_io[36] | |
| usb1.1 | usb_dn | digital_io[37] | |
Riscduino is a Dual 32 bit RISC V based SOC design pin compatible to arudino platform and this soc targetted for efabless Shuttle program. This project uses only open source tool set for simulation,synthesis and backend tools. The SOC flow follow the openlane methodology and SOC environment is compatible with efabless/carvel methodology.
D1
processor
sky130A