This submission is for Ibtida-I which was selected for the First MPW Shuttle. Due to the issues...
NALINKUMAR S | https://www.vlsisystemdesign.com/
This project focuses on design of a Current Starved VCO using Google Skywater (sky130)...
Madhuri Hemant Kadam | http://www.vlsisystemdesign.com/
CMOS OPAMP is Basic building block of analog and Mixed signal circuits. It is used in many...
Matthew Guthaus | https://vlsida.soe.ucsc.edu/
This project contains a test chip for several OpenRAM memory configurations. The configurations...
3v3 comparator with 1v8 output. For possible future uses in ADCs. May also include other related...
A template SoC for Google sponsored Open MPW shuttles for SKY130
Sameer S Durgoji | https://www.vlsisystemdesign.com/
Design of a 10 Bit Potentiometric Digital to Analog Converter with 3.3V analog voltage, 1.8V...
Basic design to familiarize with this service
CAN bus controller and teaching-oriented CPU core
Demonstration of the Fabulous FPGA design flow using the Skywater 130 process. This project...
VSDMemSoC is a small SoC including a RISCV-based processor named RVMYTH and an external 1kB SRAM...
This project focuses on design of a Sziklai Pair Amplifier using Google Skywater (sky130)...
Mufutau Akuruyejo | httpS://WWW.vlsisystemdesign.com
VSDBabySoC is a small SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
Project instantiates HyperRAM driver for external memory chip (8MB version) and additional...
This is a Analog to Digital Converter based on the popular SAR architecture. It has 8-bit...
Key value store implemented on asic.
A attempt to integrate various peripherals like I2C, I2S, UART, SPI, QSPI , JTAG, PWM, GPIO ,...
This project is intended to implement a closed-loop class-d audio amplifier with 1.8 V power...
Omar Mohamed Saadawy
Voltmeter & Ammeter
ROHINTH RAM R.V. | https://www.vlsisystemdesign.com/
Two Stage CMOS Operational Amplifier
MBIST controller with Row Redundancy Support
Sudoku accelerator module that is capable of running an 'only candidate' pass in 23 cycles and a...
This projects aims to design an high speed adder based on recursive doubling technique and...
Reduced version of TreePRAM for faster builds and tests. Not submitting for the shuttle.
A reconfigurable logic circuit made of identical rotatable tiles.
Implements a version of the parallel random-access machine used in theoretical computer science...
Yuki Azuma | https://cpu-dev.github.io/
PicoRV & Jacaranda-8 - It's a hobby heterogeneous processor!
This project is a light version of the Elpis core, which is a 5-stage pipelined and multi-cycle...
Philipp Gühring | https://libresilicon.com/
This is a testwafer project with standard cells that were automatically generated by the...
This project implements a pre-trained neural network for hand-written digits from MNIST dataset.
Five photodetector layout by sky130 PDK 1. Simple p-n photodiode. 2. Buried double junction...
Random number generators, PUFs, and resubmission of MPW-1 Softshell.
Abdullah YILDIZ | https://yongatek.com/
YONGA-100M Ethernet is based on the implementation of Alex Forencich's 100Mbps Ethernet design.
Abdullah YILDIZ | https://yongatek.com/
YONGA-SERV Accelerator includes the award-winning SERV RISC-V processor with a matrix...
SHA/AES accelerator and VGA graphics demo
S Skandha Deepsita
This project is implementation of approximate multiplier published in ACM TODAES journal 2021,...
Shon Taware | https://vlsisystemdesign.com/
Aims at design of a SRAM cell array with a configuration of 1.8 V operating voltage and access...
Sebastian Wiebking | https://www.idpro-online.de
Digital test design with simple GPIO control for toolchain testing
The project instantiates an SRAM block in the user project area for testing.
Mohammad Khalique Khan | https://www.vlsisystemdesign.com/
This project produced a clean GDSII Layout with all details that are used to print photomasks...
Arduino compatible Risc-V Based SOC
A Devipriya | https://www.vlsisystemdesign.com/
This project produces a clean GDS - Final Layout with all details that are used to print...
Zain Rizwan Khan
An implementation of the original Ghazi SoC (https://efabless.com/projects/20) hardened using...
Dadda multiplier is a type of binary multiplier which uses less munber of gates when compared to...
Nicholas R. Smith
ASIC designed to translate input from the Donkey Kong Jungle Beat bongos into PS2 keystrokes.
Test SoC using Coriolis for PnR with Amaranth on Sky130
This project is implementation for conversion of 19bit fixed point number to single precision...