Nguyen Dao
Demonstration of the open FABulous eFPGA using the OpenLane flow.
Myrtle Shah
VexRiscv+SPI flash+HyperRAM SoC built using Coriolis & PDKMaster - WIP designed to be...
Lekan Afuye
Full ReRAM Memory banks
Tamas Hubai
Have you played Wordle on raw silicon yet?
Mauricio Alejandro Montanares Sepúlveda
process acoustics signals from 8 MEMS microphones with an extended frequency range up to 85 kHz...
Karthik Mahendra
I2C bus controller transmits 8-bit serial data to multiple targets
Harald Pretl
As a classroom project at Johannes Kepler University, we are designing a delta-sigma audio DAC,...
Rameen Anwar | https://github.com/merledu
This project is the extended version of Azadi-SoC, which includes all of the peripherals which...
Julien OURY
Christmas tree controller
Ramakrishna P.V.
This project includes two different designs submitted as part of SSCS PICO-2021. The two designs...
Dinesh Annayya
Logic BIST with Scan Chain to detect struck at fault MBIST with 4 Location Row Redundancy Support
Ryan Wans
An Automatic Gain Control (AGC) feedback-loop oriented towards baseband applications (0-600 MHz)...
Krishna Kummarapalli
This is a cascode cross coupled dynamic comparator that has good common mode performance
Serge Bazanski
Lanai-based microcontroller, implemented in Bluespec.
Georgios Tziantzioulis
A 512-LUT4 FPGA generated using PRGA (Princeton Reconfigurable Gate Array); An 8x8 array of...
Ruediger Ehlers
This is a specialized on-chip microcontroller/SoC component for performing runtime monitoring of...
Muhammad Tahir | http://uet.edu.pk
UETRV-ECore: An embedded class RISC V based Motor Control SoC
Steve Goldsmith | https://aurifexlabs.com
HyperRAM interface by Steve Goldsmith with an ACORN PRNG by Zhenle Cao.
Dario San Martin Molina | https://www.vlsisystemdesign.com/
3GHz High Speed VCO
Shantan Kajjam
Learning to learn
Nalinkumar S
Voltage to Time converter are mainly used in Analog to digital converter (ADCs). In this type...
Barak Hoffer
Testing ReRAM structures
Gal Nadrag
Asynchronous Fibonacci counter using two phase dual rail logic
Matt Venn | https://zerotoasiccourse.com
Zero to ASIC course group submission MPW5
Wisla Milena Morais de Oliveira
Blocks from a receiver.
Andrew Foote
an MCS-4 clone (4004, 4001, 4002)
Jorge Marin
Time-based capacitive sensor interface using highly-digital custom building blocks
Shivani Shah
We have integrated a smaller version of the 4-way set associative 256B L1 cache as user project...
Simon Waid
This project implements a low-noise high bandwidth (~1GHz) transimpedance amplifier (TIA). The...
Mehmet Fatih Gülakar | https://tutel.bilgem.tubitak.gov.tr/home
An implementation of rasterization engine using Skywater 130 nm PDK.
Matt Venn
Zero to ASIC MPW3 rerun on MPW5
Matt Venn
Zero to ASIC MPW2 rerun on MPW5
Joshua Stevens
A phased PWM controller for micro motor control
Adithya Sunil Edakkadan
2.87 GHz microwave signal generator with a small programmable sweep step size.
Maximo Balestrini
Hardware implementation of the Hack Computer from the Nand to Tetris courses
Barry Muldrey | https://gitlab.com/um-ece/ftl-lab/bemosc/mpw5-analog-chaotic-trng
Analog chaotic oscillator forming the basis of compact TRNG
Barry Muldrey | https://gitlab.com/um-ece/ftl-lab/bemosc/mpw5-digital-chaotic-trng
Discrete time-discrete value iterated chaotic map-based (T)RNG
Sahil Shah | https://www.umd.edu/
Mixed signal circuits for analog synapses.
Anton Blanchard
Microwatt is a 64 bit OpenPOWER core written in VHDL. It includes an IEEE 754 double-precision...
Arman A.
armleo_gpio is a input output IP that is designed to handle 12pF @ 100MHz. The common usage of...
Yahya Can Tuğrul
RISC-V SoC
Matt Venn
Zero to ASIC MPW4 rerun on MPW5
Anurag Dhungel
This is my test. I will be submitting thorugh my university.
Dinesh Annayya
Riscduino with Dual RISC V 32bit core
Hugo Dias Giló | https://ufersa.edu.br/
This design contains an ASK Modulator that outputs signals in the 2.4GHz band and an impedance...
Veerendra S Devaraddi
We design a 2-D systolic array architecture as shown in teh figure. Each node is a Processing...
Dinesh Annayya
A arduino pin compatible Single RISCV 32 Bit core Project
Alexander Anderson
practice
Lena Hwang
Simple vexriscv based SoC
Brandon Ong
Small hand-drawn NAND flash array.
Krishna Kummarapalli
This is a novel dynamic comparator design which improves the common mode performance
surya sunil
test
KASHIF INAYAT | https://kashifinayat.com/
This is a factored MAC, in which we have designed the factored Radix-8 Booth Multiplier (16...
Supratim Das
A simple 8bit CPU along with peripherals like vga/ps2 mouse/uart etc
Mathieu Drapeau
foobar
Jeff DiCorpo
Open FPGA
Maher Benhouria
A low power 8-bits SAR ADC based on a capacitive DAC.
Burak Aykenar
We are designing a RISC-V SoC named "MYST-IC" which is compatible to RV64IMC for a design...
Mehdi Saligane
Automated Test scribes for cryogenic PDK generation and SPICE models enhancements using...
Andrej Čižmárik
Test project
Connie Duong
Improving WEH systems through voltage boosting and component sharing
Jorge Marin
Time-based capacitive sensor interface using highly-digital custom building blocks
Dinesh Annayya
Riscduino is a Quad 32 bit RISC V based SOC design pin compatible to arudino platform and this...
Alexander Monakhov | https://engineering.phys.msu.ru/en/
Next step of Uranus FPGA project with sophisticated LUT, BRAM and IO.
Adithya Sunil Edakkadan
2.87 GHz varactor based ring oscillator
Shumpei Kawasaki | http://www.swhwc.com/
An application specific RISC-V microcontroller, MARMOT, was developed from a total scratch to a...
Staf Verhaegen
Test for PDKMaster based single port SRAM block
Onur Karataş
In this study, a digital RNG based on chaotic oscillators was implemented using the SKY130 process node.
Zbigniew Drozd
Two small demos for sky130. - rendering circuit for three blobs - playable tetris...
Derek Hines-Mohrman | https://www.bsg.ai/
Test chip for a DDR3 SSTL driver. This chip will evaluate the performance of this this...