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MPW-5 Shuttle Projects

FABulous_eFPGA public

Nguyen Dao

Demonstration of the open FABulous eFPGA using the OpenLane flow.

Coriolis Test... public

Myrtle Shah

VexRiscv+SPI flash+HyperRAM SoC built using Coriolis & PDKMaster - WIP designed to be...

ReRAM Array Test public

Lekan Afuye

Full ReRAM Memory banks

Asicle public

Tamas Hubai

Have you played Wordle on raw silicon yet?

Microwave-Signal-... public

Adithya Sunil Edakkadan

2.87 GHz microwave signal generator with a small programmable sweep step size.

SonaronChip-8 public

Mauricio Alejandro Montanares Sepúlveda

process acoustics signals from 8 MEMS microphones with an extended frequency range up to 85 kHz...

I2C Controller public

Karthik Mahendra

I2C bus controller transmits 8-bit serial data to multiple targets

Delta-Sigma... public

Harald Pretl

As a classroom project at Johannes Kepler University, we are designing a delta-sigma audio DAC,...

Azadi_III public

Rameen Anwar | https://github.com/merledu

This project is the extended version of Azadi-SoC, which includes all of the peripherals which...

ChristmasTreeController public

Julien OURY

Christmas tree controller

PICO Design... public

Ramakrishna P.V.

This project includes two different designs submitted as part of SSCS PICO-2021. The two designs...

PWM public

Serdar Ünal | https://tutel.bilgem.tubitak.gov.tr/

PWM (Pulse Width Modulation) module


Dinesh Annayya

Logic BIST with Scan Chain to detect struck at fault MBIST with 4 Location Row Redundancy Support

Baseband-Inductor... public

Ryan Wans

An Automatic Gain Control (AGC) feedback-loop oriented towards baseband applications (0-600 MHz)...

CMOS Dynamic Comparator public

Krishna Kummarapalli

This is a cascode cross coupled dynamic comparator that has good common mode performance

qf105 public

Serge Bazanski

Lanai-based microcontroller, implemented in Bluespec.


Georgios Tziantzioulis

A 512-LUT4 FPGA generated using PRGA (Princeton Reconfigurable Gate Array); An 8x8 array of...

Runtime... public

Ruediger Ehlers

This is a specialized on-chip microcontroller/SoC component for performing runtime monitoring of...

UETRV-ECore public

Muhammad Tahir | http://uet.edu.pk

UETRV-ECore: An embedded class RISC V based Motor Control SoC

Pseudo-Secure Memory public

Sukru Uzun | https://procenne.com/

SRAM based pseudo-secure memory.

PSRAM Interface with... public

Steve Goldsmith | https://aurifexlabs.com

HyperRAM interface by Steve Goldsmith with an ACORN PRNG by Zhenle Cao.

high_speed_vco public

Dario San Martin Molina | https://www.vlsisystemdesign.com/

3GHz High Speed VCO

Chip design training public

Shantan Kajjam

Learning to learn

ALU public

Janani Aravind | https://www.ncat.edu/

Digital design that compares the ALU results

Voltage to Time Converter public

Nalinkumar S

Voltage to Time converter are mainly used in Analog to digital converter (ADCs). In this type...

ReRAM Test public

Barak Hoffer

Testing ReRAM structures

Asynchronous... public

Gal Nadrag

Asynchronous Fibonacci counter using two phase dual rail logic

Zero to ASIC... public

Matt Venn | https://zerotoasiccourse.com

Zero to ASIC course group submission MPW5

Receiver Blocks public

Wisla Milena Morais de Oliveira

Blocks from a receiver.

4ft4 public

Andrew Foote

an MCS-4 clone (4004, 4001, 4002)

PLL-based... public

Jorge Marin

Time-based capacitive sensor interface using highly-digital custom building blocks

mpw5_cache public

Shivani Shah

We have integrated a smaller version of the 4-way set associative 256B L1 cache as user project...

TIA-for-physic-ex... public

Simon Waid

This project implements a low-noise high bandwidth (~1GHz) transimpedance amplifier (TIA). The...

Raster_engine public

Mehmet Fatih Gülakar | https://tutel.bilgem.tubitak.gov.tr/home

An implementation of rasterization engine using Skywater 130 nm PDK.

Zero to ASIC... public

Matt Venn

Zero to ASIC MPW3 rerun on MPW5

Zero to ASIC... public

Matt Venn

Zero to ASIC MPW2 rerun on MPW5

ActuatorController public

Joshua Stevens

A phased PWM controller for micro motor control

Hack SoC public

Maximo Balestrini

Hardware implementation of the Hack Computer from the Nand to Tetris courses

Analog Chaotic... public

Barry Muldrey | https://gitlab.com/um-ece/ftl-lab/bemosc/mpw5-analog-chaotic-trng

Analog chaotic oscillator forming the basis of compact TRNG

Digital Chaotic... public

Barry Muldrey | https://gitlab.com/um-ece/ftl-lab/bemosc/mpw5-digital-chaotic-trng

Discrete time-discrete value iterated chaotic map-based (T)RNG

Mixed_signal_circuits public

Sahil Shah | https://www.umd.edu/

Mixed signal circuits for analog synapses.

Microwatt MPW5 public

Anton Blanchard

Microwatt is a 64 bit OpenPOWER core written in VHDL. It includes an IEEE 754 double-precision...

armleo_gpio_mpw5 public

Arman A.

armleo_gpio is a input output IP that is designed to handle 12pF @ 100MHz. The common usage of...

kasirga-c0-mpw-5 public

Yahya Can Tuğrul


Zero to ASIC... public

Matt Venn

Zero to ASIC MPW4 rerun on MPW5

Test public

Anurag Dhungel

This is my test. I will be submitting thorugh my university.

Riscduino-DCore public

Dinesh Annayya

Riscduino with Dual RISC V 32bit core

ASK Modulator... public

Hugo Dias Giló | https://ufersa.edu.br/

This design contains an ASK Modulator that outputs signals in the 2.4GHz band and an impedance...

Systolic_array public

Veerendra S Devaraddi

We design a 2-D systolic array architecture as shown in teh figure. Each node is a Processing...

Riscduino-SCore(S2) public

Dinesh Annayya

A arduino pin compatible Single RISCV 32 Bit core Project

practice public

Alexander Anderson


junga_soc_mpw5 public

Lena Hwang

Simple vexriscv based SoC

NAND Flash MPW-5 public

Brandon Ong

Small hand-drawn NAND flash array.

CMOS Dynamic... public

Krishna Kummarapalli

This is a novel dynamic comparator design which improves the common mode performance

Test public

surya sunil


Factored MAC for... public

KASHIF INAYAT | https://kashifinayat.com/

This is a factored MAC, in which we have designed the factored Radix-8 Booth Multiplier (16...

NoobsASIC public

Supratim Das

A simple 8bit CPU along with peripherals like vga/ps2 mouse/uart etc

xyz public

M. Shalan | http://efabless.com


Open FPGA public

Jeff DiCorpo


8-bits SAR ADC public

Maher Benhouria

A low power 8-bits SAR ADC based on a capacitive DAC.

mystic_peripherals public

Burak Aykenar

We are designing a RISC-V SoC named "MYST-IC" which is compatible to RV64IMC for a design...

OpenFASOC-cryo-gen public

Mehdi Saligane

Automated Test scribes for cryogenic PDK generation and SPICE models enhancements using...

Test project public

Andrej Čižmárik

Test project

WirelessEnergyHarvesting public

Connie Duong

Improving WEH systems through voltage boosting and component sharing

PLL-based... public

Jorge Marin

Time-based capacitive sensor interface using highly-digital custom building blocks

Riscduino-QCore public

Dinesh Annayya

Riscduino is a Quad 32 bit RISC V based SOC design pin compatible to arudino platform and this...

Miranda eFPGA public

Alexander Monakhov | https://engineering.phys.msu.ru/en/

Next step of Uranus FPGA project with sophisticated LUT, BRAM and IO.

VCO public

Adithya Sunil Edakkadan

2.87 GHz varactor based ring oscillator

Power Monitoring... public

Shumpei Kawasaki | http://www.swhwc.com/

An application specific RISC-V microcontroller, MARMOT, was developed from a total scratch to a...

SRAMTestVehicle public

Staf Verhaegen

Test for PDKMaster based single port SRAM block

RNG-CHAOS public

Onur Karataş

In this study, a digital RNG based on chaotic oscillators was implemented using the SKY130 process node.

TETRIS on silicon public

Zbigniew Drozd

Two small demos for sky130. - rendering circuit for three blobs - playable tetris...

DDR3-SSTL-Test public

Derek Hines-Mohrman | https://www.bsg.ai/

Test chip for a DDR3 SSTL driver. This chip will evaluate the performance of this this...