This is a simple, microcontroller-style SoC based around a Lanai core.

Lanai is a ~mysterious~ RISC core that happens to have an LLVM target, and to which I've succesfully ported rustc (to be upstreamed). The core implementation is quite spartan: 3-stage, in-order. Currently targeting a 50MHz fclk.

Around the core, we have a Wishbone interconnect off of which we plan to hang a bunch of peripherals. Currently, only SPI and GPIO are implemented.

The entire project is implemented in Bluespec, which is an industry standard high-level HDL that recently had its reference compiler opensourced. The structural Verilog comes from an external repository, which has a fully reproducible build implemented using Bazel and Nix.