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qf105

public project

This is a simple, microcontroller-style SoC based around a Lanai core.

Lanai is a ~mysterious~ RISC core that happens to have an LLVM target, and to which I've succesfully ported rustc (to be upstreamed). The core implementation is quite spartan: 3-stage, in-order. Currently targeting a 50MHz fclk.

Around the core, we have a Wishbone interconnect off of which we plan to hang a bunch of peripherals. Currently, only SPI and GPIO are implemented.

The entire project is implemented in Bluespec, which is an industry standard high-level HDL that recently had its reference compiler opensourced. The structural Verilog comes from an external repository, which has a fully reproducible build implemented using Bazel and Nix.

If you are collaborating on this project, please click here to access your collaboration files, and click "Accept Share" in the actions column if you haven't done so already.

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Owner

Serge Bazanski

Summary

Lanai-based microcontroller, implemented in Bluespec.

Version

1.0

Category

processor

Process

sky130A

Last MPW Precheck

Succeeded

03/21/22 12:28:28 PDT

Last Tapeout

Succeeded

04/27/22 16:57:35 PDT