Mayank Varshney | https://github.com/mbits-mirafra/efabless
FPU design implemented by Mirafra Team
Emilio Baungarte
eFPGA of 80 CLB developed with openFPGA, and implemented with 130nm
William (Liam) Oswald
University of South Alabama Custom SRAM project 03. This project includes a 32x1024 Truncation...
Tim Edwards
First test chip of Chipalooza projects
Uri Shaked | https://tinytapeout.com/
Tiny Tapeout 06 - Visit https://tinytapeout.com for more information on the project and how to...
Jian Ramark Maranan
Testing the Analog Design Flow for 6 DFFs design.
Jian Ramark Maranan
Testing the Digital Design Flow for a Full Adder design.
Sanee Aman
Traffic Light Controller
Shashank Sharma
Async D Flip-Flop (DFF) is a digital circuit element in electronics. Unlike synchronous DFF, it...
VISHNU BHARADWAJ BALASUBRAMANYA GARGESHWARI
Dual Port Ram
Spurthi Malode
1:8 demux
ripple_counter design
Matt Venn
timer demonstration
S R RISHAB KUMAR 2022 Batch,PES University | https://github.com/SR-Rishab/Divider_tape_out.git
GDSII of a structural 32-bit unsigned divider
Tapeout Program
YAGNA VIVEK B
A 32 bit ladner fischer adder that can significantly reduce delay when compared to traditional adders
Ms. Spoorthi S
Plant Watering system is a digital design that takes moisture sensor as the input and decides...
Vaishnavi B V
tflipflop tapeout
Lalith Lochan
Fibonacci_sequence_calculator
Srinidhi
The shift register that uses parallel input and generates serial output is known as the parallel...
Akarsh Hegde
pes_full_subtractor_tapeout
Sepideh Asgari | https://github.com/EMIL-YORKU/SeqSoc_Chipalooza.git
Our project aims to revolutionize DNA sequencing technology by developing a cutting-edge System...
ROHITH D N
Baud rate generator tapeout repo
IVO GAY CARAMUTI
demostration proyect
Mohamed Kassem
BLA
IVO GAY CARAMUTI | https://github.com/efabless/caravel_user_project
this is a test to do the Submitting Precheck and Tapeout Jobs
Manish Mahajan
NR 5G 2_0_4 BG2
Mohamed Tawfik
test zam_zerotoasiccourse_test_01 SHA256