Govindu Sathvik Reddy | https://iiti.ac.in/
Developed a 16bit processor having its own Reduced Instruction Set with least possible number of...
PANKAJ AGRAWAL | http://www.vlsisystemdesign.com/
This project is about 8 bit bidirectional counter which s controlled by control signal. As name...
Anmol Shetty | https://www.vlsisystemdesign.com/
This project simulates a synchronous FIFO where data is written in a sequential manner into a...
Sepideh Asgari
Nanopore-based DNA sequencing is a unique, scalable technology, utilized to identify nucleotides...
Anuj Kumar Jha | https://www.vlsisystemdesign.com/
In this project, Mealy based non overlapping sequence detector is implemented to detect 1010...
Aditya Nagaraj | https://rvce.edu.in
8 bit modified fixed point baugh wooley multiplier, following Q5.3 representation
Subash Polisetty
Register which performs various options based on a control input
Maximilien Dagois
Mask ROM of a game boy sample + LFSR for use on address 0x2001 to 0x20FF.
Praneeth | https://www.iiitdm.ac.in/
Implementing the matrix operation of 16-point Walsh Transform using 8-bit inputs.
Daniel J Wisehart
Basic grey counter.
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
pro_row_idct_folded
Jay shah | www.vlsisystemdesign.com
This project simulates the designed UART Transmitter module which is used to transmit a data...
Siddhant Nayak | https://www.vlsisystemdesign.com/
In this project, a vending machine with change system using Verilog HDL is proposed based on...
Sritam Birtia | https://www.vlsisystemdesign.com/
The main goals of this project are implementing an 8-bit bcd code counter in skywater 130nm and...
Alexander Shabarshin
This is a test circuit for 3-rail async ternary selector that connects one of the 3 ternary...
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
pro_row_idct_parallel
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
Implementation of 16-bit-Han-Carlson Adder, a parallel prefix fast adder using Sky130nm PDK.
Uri Shaked | https://tinytapeout.com
Re-run of TinyTapeout 02 with an extra SkullART slot
Aman Prajapati | https://www.vlsisystemdesign.com
A Johnson counter is a modified ring counter in which the output from the last flip flop is...
Joseph Riem
GWU's project to verify gds file using efabless precheck and tapeout check.
Tejas B N | https://www.vlsisystemdesign.com/
Gray code counter is a digital counter that counts such that each successive bit patterns...
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
Implementation of 16-bit-Ladner-Fischer-Adder, a parallel prefix fast adder using Sky130nm PDK.
ritesh lalwani | https://www.vlsisystemdesign.com/
The Aim of this exercise is to design a linear feedback shift register to produce a random...
Takuya Sasatani | https://www.takuyasasatani.com/
Generates multiple clocks and outputs the selected clock
Yukidamayaki
Resubmission
Andrea Mifsud
An aggressively designed core ReRAM cell with a pitch of 1.08um x 1.56um. The main objective is...
Janani Aravind
Radiation Hardened ALU
LOKESH MAJI | https://www.vlsisystemdesign.com/
In this project, traffic light controller on a four-way road using a sensor is proposed. A...
Himanshu Rai | https://www.vlsisystemdesign.com/
this project is about pwm generator with a feature of variable duty cycle .
Yash Kothari | https://www.vlsisystemdesign.com/
LIFO buffers are a contiguous piece of memory that require special methods to add and remove data.
Paras Vekariya
This project simulates the overlapping Moore Design for Sequence Detection where it toggles the...
Chithambara Moorthii J
The project includes RRAM In Memory Computing Accelerator , designed by our team at IIT...
Matt Venn | https://www.zerotoasiccourse.com/
Zero to ASIC course group submission for MPW8
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
hada_2d1_3
Sahil Mahajan | www.vlsisystemdesign.com
Physical Design of a 4 bit bidirectional counter
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
Implementation of 16-bit-Kogge-Stone-Adder, a parallel prefix fast adder using Sky130nm PDK.
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
mcm_8outputs
ADITYA SINGH | https://www.vlsisystemdesign.com/
serial in parallel out shift register
Ujjawal Sharma | https://www.vlsisystemdesign.com/
A bidirectional counter is a sequential up/down That has the ability to count in both directions...
Praneeth | https://iiitdm.ac.in/
Conventional lifting based 9/7 DWT using direct implementation.
Archan Desai | https://www.vlsisystemdesign.com/
ASIC design of automatic washing machine
Jesse Cirimelli-Low | https://vlsida.soe.ucsc.edu/
This testchip includes various SRAM designs generated with OpenRAM, an open srouce memory...
Praneeth | https://iiitdm.ac.in/
32-point proposed Integer DCT using parallel architecture, odd_even_parallel_complete
Praneeth | https://iiitdm.ac.in/
Conventional 13X13 proposed N-parallel (5,3) lifting based 2D DWT
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
mcm_resource
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
integer_mcm
Hari V
fastmul_32x32
Ruige Lee
This is the simplest version of Rift2Core. Rift2300 has no L2 cache, no L1 ICache, no L2 TLB, no...
Praneeth | https://iiitdm.ac.in/
Conventional accumulator based 2D parallel architecture (N-outputs at a time), area and...
Uriel Jaramillo Toral | https://unidad.gdl.cinvestav.mx/
Decrypt AES 128, using skywater 130nm technology, which will serve as part of a master's thesis...
Arya Reais-Parsi | https://eecs.berkeley.edu
Stamps out BFG-generated 4-LUTs to measure their performance.
Radheshyam Sharma | https://iiti.ac.in/
Matrix multiplication is probably the most important matrix operation. It is used widely in such...
Nishad Potdar
This is an implementation of BCD to Seven Segment Decoder. The module takes 4 bit BCD input and...
Roman Bacik
USB to UART converter
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
Implementation of 16-bit-Sklansky-Adder, a parallel prefix fast adder using Sky130nm PDK.
Vrushabh Damle
This is an implementation of a 4-bit carry look-ahead adder which is a fast adder. It has two...
Abdul Moiz Sheikh
The aim of project is to design a co-processor for floating point arithmetic and encryption...
Mehdi Saligane
Test Structures for NIST's Nanofabrication Project
| https://www.vlsisystemdesign.com
A parking ticket vending machine based on FSM, implemented using verilog.
Mehdi Saligane
Test harness for MEMS sensing
Leo Moser
A very simple SoC
priyanshu | https://www.vlsisystemdesign.com/
Shift registers are some sort of sequential logic circuitries that are majorly deployed to store...
Anirudh Sivaraman
Test project with minimal changes to caravel_user_project
Carl L Brando | https://www.umd.edu
We are planning to make a Mixed signal in-memory compute ReRAM arrray. This takeout will allow...
Deepak verma | https://home.iitd.ac.in/
SRAM in memory computing : The project includes SRAM In Memory Computing Accelerator. This is...
Luca Horn
First attempt at a Microcontroller, featuring a 4-bit CPU with re-programmable microcode....
Praneeth | https://iiitdm.ac.in/
DWT - Conventional 5/3 lifting based wavelet with 3 octaves.
Dinesh Annayya
This is chip is add-on to our Riscduino SCORE/DCORE/QCORE Chip set. As there are no free space...
David Zheng
I am trying to implement a design which downconverts a 27MHz signal to 1MHz. This is my first...
Uriel Jaramillo Toral | https://unidad.gdl.cinvestav.mx/
This is the comparison project of the projects of the CINVESTAV GUADALAJARA community. The...
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
biquad_iir_ext
Zexi Liu
Lab-on-chip test IC
Jan Gray | http://fpga.org
S3GA: simple scalable serial FPGA. An area-efficient hierarchical FPGA core with serial logic...
Praneeth
Conventional convolution based folded DWT using Recurse 46, 32-bit Wallace tree multiplier
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
DCT4_PAR_2D
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
iir2_direct
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
IIR-Filter-using-Baugh-Wooley-Multipler
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
dct4_par_2d
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
dct8_par_2d
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
radix2_parallel
Maximo Balestrini
Peripherals tests for future SoC targeting Micro/Circuit Python
Praneeth | https://iiitdm.ac.in/
Conventional convolution based folded DWT using Recurse 35 and 32-bit Wallace tree multiplier
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
iir2_1multi_ext
Piotr Wegrzyn
Pipelined cpu with custom architecture
YERRA BHASKARA VARA PRASAD
The smart glove transforms the hand signals to text and to speech by utilizing Arduino voice...
Furkan Ciylan
Implementation of SHA 3 Encrytion algorithm on caravel using skywater 130nm technology.
Andrea Mifsud
A replica of the nominal project with a significant difference - main objective is...
Po-Chun Huang
This project contains array of various sizes of 1T1R devices and a 1T1R 256x256 ReRAM module for...
Philipp Gühring | https://libresilicon.com/
Test Structures for Sky130 generated by DanubeRiver
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
iir6_multi_ext
Praneeth | https://www.iiitdm.ac.in/
Implementing the matrix operation of 16-point Hadamard Transform using 8-bit inputs.
Govindu Sathvik Reddy | https://iiti.ac.in/
Developed a 16bit processor having its own Reduced Instruction Set with least possible number of...
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
iir6_cascade
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
iir6_direct
Neha Maheshwari
arbiter puf
Talha Bin Azmat | http://isb.nu.edu.pk/rfcs2/
This project consists of a DNN accelerator which used cross bar array to perform in-memory...
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
iir6_multi_delay
Thorsten Knoll
Hardware circuit with an VGA output that displays a simple clock on the screen.
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
six_iir_ext
Zhiyang Ong | https://github.com/eda-ricercatore
Many types of hardware accelerators for machine learning have been proposed, such as those based...
MAKAM MANIKYA RAKSHITH
Serial Adder
Sean "xobs" Cross
Wishbone PIO is an implementation of the PIO block attached to the Wishbone bus. A PIO block is...
AASHISH TIWARY | https://www.vlsisystemdesign.com/
Arithmatic Logic Unit ALU is a processor unit which performs the task of addition, subtraction,...
S Skandha Deepsita
This project is an implementation of approximate adder for error tolerant multimedia...
Soumil Jain | https://isn.ucsd.edu/courses/beng207/
ReRAM 16x16 array characterisation, including forming, incremental set and reset, and parallel...
Rakshit Bhatia | https://www.vlsisystemdesign.com/
The universal shift register features parallel load, left-shift and right-shift serial input,...
Mathis Salmen
SoomRV testing resubmission for MPW-8!
Paras Vekariya | VSD-IAT
This project simulates the overlapping Moore Design for Sequence Detection where it toggles the...
Raj kachhadiya | www.vlsisystemdesign.com
The information stored within these registers can be transferred with the help of shift...
Nishit Chechani | https://www.vlsisystemdesign.com/
The project below illustrates how an elevator controller can be designed for as many floors as...
Julien OURY
Christmas tree controller (MPW5 ReRun)
Shashank Singh Rawat | https://iiti.ac.in/
This is a dual MAC unit with a single activation function.
Muhammad Usama Zubair | https://github.com/ee-uet
Slightly modified version of UETRV_ESoC, a RISC-V based Embedded class SoC integrating 3-stage...
Harald Pretl | https://iic.jku.at
We have implemented mixed signals blocks: A SAR-ADC with 12b and OSR=1...256 (decimation filter...
NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/
Implementation of 16-bit-Brent-Kung-Adder, a parallel prefix fast adder using Sky130nm PDK.
Hari V
fastmul_16x16
Tamas Hubai
Universal logic gates, self-documenting version
Komal Gupta | https://iiti.ac.in/
Dadda proposed a method of reduction which achieves the reduced two-rowed Partial products in a...
Paweł Sitarz
Project instantiates HyperRAM controller for external memory chip (8MB version) connected to...
Staf Verhaegen
Iteration on SRAM test vehicle that failed to be selected for MPW5, MPW6 and MPW7.
MERL SoC-Now | https://github.com/merledu
This SoC is generated by the SoC Now Generator. It is written in Chisel.
Dinesh Annayya
Riscduino is a Dual 32 bit RISC V based SOC design pin compatible to arduino platform and this...
Dinesh Annayya
Arduino pin compatible Single RISCV 32 Bit core Project
Ruige Lee
This is an almost full-functional version of Rift2Core. Rift2330 has the smallest L2 cache, L1...
Julien OURY
Generic SoC
S Skandha Deepsita
The sum of products circuits with four 8-bit inputs, approximate multiplier and approximate...
Noah Wood | spookymfg.com
Libre-QASIC is an experimental open-source chip implementing a linear optical quantum computing...
Tobias Strauch
RISC-V based MiniSoC supporting Wave-Pipelined Dynamic Interleaved-Multi-Threading
Ruige Lee
This is a simple version of Rift2Core. Rift2320 has a small L2 cache, L1 Cache(Much Bigger than...
Anton Blanchard
Microwatt is a 64 bit OpenPOWER core written in VHDL. It includes an IEEE 754 double-precision...
i212435 Shaheer Ashraf | http://isb.nu.edu.pk/rfcs2/
This is a proposal for IEEE PICO design contest. A Matrix Multiplier based on Systolic Array...
Dinesh Annayya
Riscduino is a Quad 32 bit RISC V based SOC design pin compatible to arduino platform and this...
Shumpei Kawasaki | www.swhwc.com
Our submission to Google sponsored open source shuttle consists of a 2-stage pipeline SH-2 CPU...