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MPW-8 Shuttle Projects

16bit-pipelined-R... public

Govindu Sathvik Reddy | https://iiti.ac.in/

Developed a 16bit processor having its own Reduced Instruction Set with least possible number of...

caravel_iiitb_bidicntr public

PANKAJ AGRAWAL | http://www.vlsisystemdesign.com/

This project is about 8 bit bidirectional counter which s controlled by control signal. As name...

iiitb_sfifo public

Anmol Shetty | https://www.vlsisystemdesign.com/

This project simulates a synchronous FIFO where data is written in a sequential manner into a...

unigate-sky public

Tamas Hubai

Universal logic gates, self-documenting version

Mixed-Signal SoC... public

Sepide Asgari

Nanopore-based DNA sequencing is a unique, scalable technology, utilized to identify nucleotides...

Modified Baugh... public

Aditya Nagaraj | https://rvce.edu.in

8 bit modified fixed point baugh wooley multiplier, following Q5.3 representation

iiitb_sqd_1010 public

Anuj Kumar Jha | https://www.vlsisystemdesign.com/

In this project, Mealy based non overlapping sequence detector is implemented to detect 1010...

IIITDMK_16-point... public

Praneeth | https://www.iiitdm.ac.in/

Implementing the matrix operation of 16-point Walsh Transform using 8-bit inputs.

universal-shift-register public

Subash Polisetty

Register which performs various options based on a control input

gbcart public

Maximilien Dagois

Mask ROM of a game boy sample + LFSR for use on address 0x2001 to 0x20FF.

IIITDMK_pro_row_i... public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

pro_row_idct_folded

grey_codes public

Daniel J Wisehart

Basic grey counter.

iiitb_uarttx_mpw8 public

Jay shah | www.vlsisystemdesign.com

This project simulates the designed UART Transmitter module which is used to transmit a data...

iiitb_vm public

Siddhant Nayak | https://www.vlsisystemdesign.com/

In this project, a vending machine with change system using Verilog HDL is proposed based on...

iiitb_cps public

Ishan Desai | https://www.vlsisystemdesign.com/

ASIC Design of Car Parking System.

TestAsyncTrimux-MPW8 public

Alexander Shabarshin

This is a test circuit for 3-rail async ternary selector that connects one of the 3 ternary...

iiitb_bcdc public

Sritam Birtia | https://www.vlsisystemdesign.com/

The main goals of this project are implementing an 8-bit bcd code counter in skywater 130nm and...

IIITDMK_pro_row_i... public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

pro_row_idct_parallel

IIITDMK_16-bit-Ha... public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

Implementation of 16-bit-Han-Carlson Adder, a parallel prefix fast adder using Sky130nm PDK.

TinyTapeout SkullART public

Uri Shaked | https://tinytapeout.com

Re-run of TinyTapeout 02 with an extra SkullART slot

iiitb_jc public

Aman Prajapati | https://www.vlsisystemdesign.com

A Johnson counter is a modified ring counter in which the output from the last flip flop is...

GWU MPW8 Verification public

Joseph Riem

GWU's project to verify gds file using efabless precheck and tapeout check.

IIITDMK_16-bit-La... public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

Implementation of 16-bit-Ladner-Fischer-Adder, a parallel prefix fast adder using Sky130nm PDK.

caravel_iiitb_lfsr public

ritesh lalwani | https://www.vlsisystemdesign.com/

The Aim of this exercise is to design a linear feedback shift register to produce a random...

iiitb_gc_mpw8 public

Tejas B N | https://www.vlsisystemdesign.com/

Gray code counter is a digital counter that counts such that each successive bit patterns...

Hardened_ALU public

Janani Aravind

Radiation Hardened ALU

clock_divide_selector public

Takuya Sasatani | https://www.takuyasasatani.com/

Generates multiple clocks and outputs the selected clock

Yatsuhashi (MPW7) public

Yukidamayaki

Resubmission

iiitb_tlc_mpw8 public

LOKESH MAJI | https://www.vlsisystemdesign.com/

In this project, traffic light controller on a four-way road using a sensor is proposed. A...

mega4_reram_nom public

Andrea Mifsud

An aggressively designed core ReRAM cell with a pitch of 1.08um x 1.56um. The main objective is...

pwm_gen public

Himanshu Rai | https://www.vlsisystemdesign.com/

this project is about pwm generator with a feature of variable duty cycle .

iiitb_lifo public

Yash Kothari | https://www.vlsisystemdesign.com/

LIFO buffers are a contiguous piece of memory that require special methods to add and remove data.

iiitb_brg public

| vlsisystemdesign.com

Chip for Baud Rate Generator

3bit_rc public

Arsh Kedia | https://www.vlsisystemdesign.com/

3 bit ring counter

SequenceDetection public

Paras Vekariya

This project simulates the overlapping Moore Design for Sequence Detection where it toggles the...

Zero to ASIC... public

Matt Venn | https://www.zerotoasiccourse.com/

Zero to ASIC course group submission for MPW8

RRAM_IMC_MPW8 public

Chithambara Moorthii J

The project includes RRAM In Memory Computing Accelerator , designed by our team at IIT...

IIITDMK_hada_2d1_3 public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

hada_2d1_3

iiitb_bc _caravel public

Ujjawal Sharma | https://www.vlsisystemdesign.com/

A bidirectional counter is a sequential up/down That has the ability to count in both directions...

IIITDMK_mcm_8outputs public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

mcm_8outputs

iiitb_sipo_mpw8 public

ADITYA SINGH | https://www.vlsisystemdesign.com/

serial in parallel out shift register

IIITDMK_16-bit-Ko... public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

Implementation of 16-bit-Kogge-Stone-Adder, a parallel prefix fast adder using Sky130nm PDK.

iiitb_4bbc public

Sahil Mahajan | www.vlsisystemdesign.com

Physical Design of a 4 bit bidirectional counter

IIITDMK_97... public

Praneeth | https://iiitdm.ac.in/

Conventional lifting based 9/7 DWT using direct implementation.

IIITDMK_32-point... public

Praneeth | https://iiitdm.ac.in/

32-point proposed Integer DCT using parallel architecture, odd_even_parallel_complete

iiitb_wm public

Archan Desai | https://www.vlsisystemdesign.com/

ASIC design of automatic washing machine

openram_testchip_mpw8 public

Jesse Cirimelli-Low | https://vlsida.soe.ucsc.edu/

This testchip includes various SRAM designs generated with OpenRAM, an open srouce memory...

IIITDMK_53... public

Praneeth | https://iiitdm.ac.in/

Conventional 13X13 proposed N-parallel (5,3) lifting based 2D DWT

IIITDMK_mcm_resource public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

mcm_resource

iiitb_sd_mpw8 public

Anshul Madurwar | https://www.vlsisystemdesign.com/

Sequence Detector Design

IIITDMK_integer_mcm public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

integer_mcm

fastmul_16x16 public

Hari V

fastmul_16x16

fastmul_32x32 public

Hari V

fastmul_32x32

Rift2Go_2300_Sky130_MPW8 public

Ruige Lee

This is the simplest version of Rift2Core. Rift2300 has no L2 cache, no L1 ICache, no L2 TLB, no...

IIITDMK_accumulat... public

Praneeth | https://iiitdm.ac.in/

Conventional accumulator based 2D parallel architecture (N-outputs at a time), area and...

Low Power... public

Ali Sabir | http://isb.nu.edu.pk/rfcs2/

A low power approximate processor for IOT intelligent edge nodes applications. The proposed...

decrypt_aes128 public

Uriel Jaramillo Toral | https://unidad.gdl.cinvestav.mx/

Decrypt AES 128, using skywater 130nm technology, which will serve as part of a master's thesis...

BFG 4-LUT Test public

Arya Reais-Parsi | https://eecs.berkeley.edu

Stamps out BFG-generated 4-LUTs to measure their performance.

IIT_Indore_MM public

Radheshyam Sharma | https://iiti.ac.in/

Matrix multiplication is probably the most important matrix operation. It is used widely in such...

SSD_MPW8 public

Nishad Potdar

This is an implementation of BCD to Seven Segment Decoder. The module takes 4 bit BCD input and...

usb2uart-mpw8 public

Roman Bacik

USB to UART converter

IIITDMK_16-bit-Sk... public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

Implementation of 16-bit-Sklansky-Adder, a parallel prefix fast adder using Sky130nm PDK.

IIITDMK_16-bit-Br... public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

Implementation of 16-bit-Brent-Kung-Adder, a parallel prefix fast adder using Sky130nm PDK.

sky130CLA public

Vrushabh Damle

This is an implementation of a 4-bit carry look-ahead adder which is a fast adder. It has two...

mega1_reram_accuracy public

Andrea Mifsud

In a typical 1T1R cell, the absolute voltage across the ReRAM device is unknown due to the...

Co-Processor-with... public

Abdul Moiz Sheikh

The aim of project is to design a co-processor for floating point arithmetic and encryption...

Nanofabrication... public

Mehdi Saligane

Test Structures for NIST's Nanofabrication Project

Fitbit Project... public

Mehdi Saligane

Test harness for MEMS sensing

iiitb_ptvm public

| https://www.vlsisystemdesign.com

A parking ticket vending machine based on FSM, implemented using verilog.

IIT_Indore_Dadda_... public

Komal Gupta | https://iiti.ac.in/

Dadda proposed a method of reduction which achieves the reduced two-rowed Partial products in a...

LeoSoC public

Leo Moser

A very simple SoC

iiitb_pipo_mpw8 public

priyanshu | https://www.vlsisystemdesign.com/

Shift registers are some sort of sequential logic circuitries that are majorly deployed to store...

IIITDMK_53... public

Praneeth | https://iiitdm.ac.in/

DWT - Conventional 5/3 lifting based wavelet with 3 octaves.

IIITDMK_dct_8 public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

dct_8

Counter project public

Anirudh Sivaraman

Test project with minimal changes to caravel_user_project

Mixed_signal_circ... public

Carl L Brando | https://www.umd.edu

We are planning to make a Mixed signal in-memory compute ReRAM arrray. This takeout will allow...

SRAM_IMC_MPW8 public

Deepak verma | https://home.iitd.ac.in/

SRAM in memory computing : The project includes SRAM In Memory Computing Accelerator. This is...

mpw-8-as1x00 public

Luca Horn

First attempt at a Microcontroller, featuring a 4-bit CPU with re-programmable microcode....

IIITDMK_dct_16 public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

dct_16

IIITDMK_biquad_iir_ext public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

biquad_iir_ext

27MHz receiver IC public

David Zheng

I am trying to implement a design which downconverts a 27MHz signal to 1MHz. This is my first...

gf180_vs_sky130 public

Uriel Jaramillo Toral | https://unidad.gdl.cinvestav.mx/

This is the comparison project of the projects of the CINVESTAV GUADALAJARA community. The...

Riscduino-pxt1 public

Dinesh Annayya

This is chip is add-on to our Riscduino SCORE/DCORE/QCORE Chip set. As there are no free space...

SLOCI2 public

Zexi Liu

Lab-on-chip test IC

S3GA public

Jan Gray | http://fpga.org

S3GA: simple scalable serial FPGA. An area-efficient hierarchical FPGA core with serial logic...

IIITDMK_dct_4 public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

dct_4

IIITDMK_DCT4_PAR_2D public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

DCT4_PAR_2D

IIITDMK_DWT... public

Praneeth

Conventional convolution based folded DWT using Recurse 46, 32-bit Wallace tree multiplier

IIITDMK_IIR-Filte... public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

IIR-Filter-using-Baugh-Wooley-Multipler

IIITDMK_dct4_par_2d public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

dct4_par_2d

eFPGA_4X4_MPW8 public

Emilio Baungarte | https://unidad.gdl.cinvestav.mx/

eFPGA_4X4_MPW8

IIITDMK_dct8_par_2d public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

dct8_par_2d

IIITDMK_radix2_parallel public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

radix2_parallel

IIITDMK_iir2_direct public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

iir2_direct

Caravel PyFive public

Maximo Balestrini

Peripherals tests for future SoC targeting Micro/Circuit Python

Shalicon public

hezixu

A fork from SoomRV-8

IIITDMK_DWT... public

Praneeth | https://iiitdm.ac.in/

Conventional convolution based folded DWT using Recurse 35 and 32-bit Wallace tree multiplier

IIITDMK_DCT_4 public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

DCT_4

IIITDMK_dct4_2d public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

dct4_2d

IIITDMK_iir2_1multi_ext public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

iir2_1multi_ext

ppcpu2 public

Piotr Wegrzyn

Pipelined cpu with custom architecture

Smart Glove public

YERRA BHASKARA VARA PRASAD

The smart glove transforms the hand signals to text and to speech by utilizing Arduino voice...

Caravel_SHA3 public

Furkan Ciylan

Implementation of SHA 3 Encrytion algorithm on caravel using skywater 130nm technology.

mega4_reram_splits public

Andrea Mifsud

A replica of the nominal project with a significant difference - main objective is...

IIITDMK_dct8_2d public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

dct8_2d

IIITDMK_iir6_multi_ext public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

iir6_multi_ext

reram_module_mpw8 public

Po-Chun Huang

This project contains array of various sizes of 1T1R devices and a 1T1R 256x256 ReRAM module for...

Sky130 Test... public

Philipp Gühring | https://libresilicon.com/

Test Structures for Sky130 generated by DanubeRiver

IIITDMK_16-point... public

Praneeth | https://www.iiitdm.ac.in/

Implementing the matrix operation of 16-point Hadamard Transform using 8-bit inputs.

IIT_INDORE_pipeli... public

Govindu Sathvik Reddy | https://iiti.ac.in/

Developed a 16bit processor having its own Reduced Instruction Set with least possible number of...

IIITDMK_iir6_cascade public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

iir6_cascade

IIITDMK_iir6_direct public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

iir6_direct

arbiter-puf public

Neha Maheshwari

arbiter puf

IIITDMK_iir6_multi_delay public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

iir6_multi_delay

ReRAM based CNN... public

Talha Bin Azmat | http://isb.nu.edu.pk/rfcs2/

This project consists of a DNN accelerator which used cross bar array to perform in-memory...

tiny_user_project... public

Thorsten Knoll

Hardware circuit with an VGA output that displays a simple clock on the screen.

IIITDMK_six_iir_ext public

NIMMAKAYALA SUMANTH GOURI MANJUNADH | https://www.iiitdm.ac.in/

six_iir_ext

HyperRAM... public

Paweł Sitarz

Project instantiates HyperRAM controller for external memory chip (8MB version) connected to...

In-Memory... public

Zhiyang Ong | https://github.com/eda-ricercatore

Many types of hardware accelerators for machine learning have been proposed, such as those based...

rvce_serial-adder public

MAKAM MANIKYA RAKSHITH

Serial Adder

Wishbone PIO public

Sean "xobs" Cross

Wishbone PIO is an implementation of the PIO block attached to the Wishbone bus. A PIO block is...

Approximate Adder AXHA public

S Skandha Deepsita

This project is an implementation of approximate adder for error tolerant multimedia...

iiitb_alu public

AASHISH TIWARY | https://www.vlsisystemdesign.com/

Arithmatic Logic Unit ALU is a processor unit which performs the task of addition, subtraction,...

ReRAM crossbar rerun public

Soumil Jain | https://isn.ucsd.edu/courses/beng207/

ReRAM 16x16 array characterisation, including forming, incremental set and reset, and parallel...

SoomRV (MPW-8) public

Mathis Salmen

SoomRV testing resubmission for MPW-8!

iiitb_usr_mpw8 public

Rakshit Bhatia | https://www.vlsisystemdesign.com/

The universal shift register features parallel load, left-shift and right-shift serial input,...

SequenceDetection1010 public

Paras Vekariya | VSD-IAT

This project simulates the overlapping Moore Design for Sequence Detection where it toggles the...

PISO(Parallel... public

Raj kachhadiya | www.vlsisystemdesign.com

The information stored within these registers can be transferred with the help of shift...

iiitb_elevator_controller public

Nishit Chechani | https://www.vlsisystemdesign.com/

The project below illustrates how an elevator controller can be designed for as many floors as...

ChristmasTreeCont... public

Julien OURY

Christmas tree controller (MPW5 ReRun)

UETRV_ESoC_v2 public

Muhammad Usama Zubair | https://github.com/ee-uet

Slightly modified version of UETRV_ESoC, a RISC-V based Embedded class SoC integrating 3-stage...

IIT_Indore_MAC_MPW8 public

Shashank Singh Rawat | https://iiti.ac.in/

This is a dual MAC unit with a single activation function.

SAR-ADC and... public

Harald Pretl | https://iic.jku.at

We have implemented mixed signals blocks: A SAR-ADC with 12b and OSR=1...256 (decimation filter...

SRAMTestVehicleG4 public

Staf Verhaegen

Iteration on SRAM test vehicle that failed to be selected for MPW5, MPW6 and MPW7.

Riscduino-DCore(D4) public

Dinesh Annayya

Riscduino is a Dual 32 bit RISC V based SOC design pin compatible to arduino platform and this...

SoC_Now public

MERL SoC-Now | https://github.com/merledu

This SoC is generated by the SoC Now Generator. It is written in Chisel.

Riscduino-SCore(S5) public

Dinesh Annayya

Arduino pin compatible Single RISCV 32 Bit core Project

Rift2Go_2330_Sky130_MPW8 public

Ruige Lee

This is an almost full-functional version of Rift2Core. Rift2330 has the smallest L2 cache, L1...

Generic_SOC_a1 public

Julien OURY

Generic SoC

Energy Efficient... public

S Skandha Deepsita

The sum of products circuits with four 8-bit inputs, approximate multiplier and approximate...

Libre-QASIC public

Noah Wood | spookymfg.com

Libre-QASIC is an experimental open-source chip implementing a linear optical quantum computing...

ShapingTheWaves_8 public

Tobias Strauch

RISC-V based MiniSoC supporting Wave-Pipelined Dynamic Interleaved-Multi-Threading

Rift2Go_2320_Sky130_MPW8 public

Ruige Lee

This is a simple version of Rift2Core. Rift2320 has a small L2 cache, L1 Cache(Much Bigger than...

Microwatt MPW8 public

Anton Blanchard

Microwatt is a 64 bit OpenPOWER core written in VHDL. It includes an IEEE 754 double-precision...

MATRIX... public

i212435 Shaheer Ashraf | http://isb.nu.edu.pk/rfcs2/

This is a proposal for IEEE PICO design contest. A Matrix Multiplier based on Systolic Array...

SH-2 BLDC motor... public

Shumpei Kawasaki | www.swhwc.com

Our submission to Google sponsored open source shuttle consists of a 2-stage pipeline SH-2 CPU...

Riscduino-QCore(Q3) public

Dinesh Annayya

Riscduino is a Quad 32 bit RISC V based SOC design pin compatible to arduino platform and this...