UETRV_ESoC_v2 is a slightly modified version of UETRV_ESoC, a RISC-V based embedded class SoC integrating 3-stage pipelined core with multiple peripherals for embedded applications. For further details with video demo, please visit the git repo.

UETRV_ESoC has previously been submitted in mpw-2, which resulted in a failed chip. It has been submitted in mpw-5 as well, but the designs before mpw-7 are likely to have timing problems. Hence, after some updates, we are re-submitting in mpw-8.