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MPW-7 Shuttle Projects

ISA 16-bit Microprocessor public

Aloke Das

This is simple microprocessor. Instruction Set Architecture (ISA). The data bus is 16 bits wide....

PRGA-test public

Sam Lim

An initial attempt to create a Test chip

Graphics Controller public

Vijayan Krishnan | https://www.chipwaretechnologies.com/

The openGFX430 is a synthesizable Graphic controller written in Verilog and tailored for the...

patmos_final_test public

Luca Pezzarossa

Test of new patmos

Waveform Generator public

Leo Moser | https://www.semify-eda.com

A generic waveform generator divided into stimulus and driver units that can be arbitrarily...

ReRAM_crossbar public

Soumil Jain | https://isn.ucsd.edu/courses/beng207/

ReRAM 16x16 array characterisation, including forming, incremental set and reset, and parallel...

Systolic Array... public

Ian Zhang

Systolic Array is a classical architecture that is recently revitalized among Neural Network...

RocketAlpha public

Nguyen Dao

This project demonstrates a customized Rocket Chip SoC, generated from Chipyard. The SoC is...

Riscduino-SCore(S4) public

Dinesh Annayya

Arduino pin compatible Single RISCV 32 Bit core Project

YONGA-CAN Controller public

Abdullah YILDIZ | https://yongatek.com/

YONGA-CAN Controller is a partial implementation of CAN 2.0B standard.

ReRAM-Controller-MPW7_v2 public

Po-Chun Huang | https://ece.umd.edu/

This project contains array of various sizes of 1T1R devices and a 1T1R 256x256 ReRAM module for...

Analog Frontend... public

Simon Waid | https://www.oeaw.ac.at/en/hephy/

This is a simple analog fronted for particle detection. The user may attach a particle detector...

SoomRV public

Mathis Salmen

SoomRV is a simple superscalar Out-of-Order RISC-V microprocessor. It can execute 4 Instructions...

FPGA_Programming_... public

Allen Boston | https://github.com/lnis-uofu

User project wrapper includes the PMU version 3, SOFA 2x2 FPGA generated using OpenFPGA, and...

Riscduino-DCore(D3) public

Dinesh Annayya

Riscduino is a Dual 32 bit RISC V based SOC design pin compatible to arduino platform and this...

Digital Biquad... public

Tiago Silva

This project contains a digital IIR biquad filter. Adapted from:...

Cryptographically... public


Cryptographically Secure RNG Design. (MPW6 resubmission)

Deprecated -... public

Zexi Liu | https://www.cmu.edu/

This project aims to build multi-purpose characterization on-chip instruments using the...

iiitb_pwm_genn public

Gopala Krishna Reddy Sanampudi | https://www.iiitb.ac.in/

Pulse Width Modulation is a famous technique used to create modulated electronic pulses of the...

FABulous_eFPGA_wb public

Nguyen Dao

This project demonstrates open source eFPGA generated by FABulous. This version is to support...

Mixed_signal_circ... public

Carl L Brando | https://umd.edu/

We have a 2x2 1T1R ReRam structure and a C4 Filter as well as some other supporting analog...

iiitb_tlc public

Maurya Patel | https://www.vlsisystemdesign.com/

A Traffic light controller made using sky130 technology node. Traffic lights are signaling...

iiitb_rv32i public

Vinay Rayapati | https://www.vlsisystemdesign.com , https://www.iiitb.ac.in

This project provides an insight into the working of a few important instructions of the...

LABS Search public

Wouter van Verre

An accelerator core for finding binary sequence with low autocorellation values

iiitb_usr public

Debangana Mukherjee | https://www.vlsisystemdesign.com/vsd-iat/

4-bit Universal Shift Register

MicroMotorSequencer public

Joshua Stevens

A phased PWM controller for micro motor control

webinar_test_1 public

Marwan Abbas

SPM example user project

rvj1-caravel-soc-mpw7 public

Jure Vreča | https://github.com/jurevreca12/rvj1-caravel-soc-mpw7

A simple SoC using the custom riscv-jedro-1 processor design.

AI-CHIP-4-IN-1 public

김태현 | https://github.com/thkim2031

In this chip there are four macros : 1. b-float FMA (16bit multiplication and 32bit...

Memory array public

Binoy B

Implementation of an 8x64 memory array

My First EF ASIC public

Larry Pearlstein | http://pearlstein.pages.tcnj.edu

Retarget FPGAs to standard cell.

Radix-2 4-bit... public

Yashwant Moses | vsdiat.com

Booth's Multiplier is based on Booth's Multiplication Algorithm. It proposes an efficient way...

SLOCI_Resubmission public

Zexi Liu | www.cmu.edu

SKYWATER Lab-on-chip IC resubmission. This project aims to build multi-purpose characterization...

iiitb_freqdiv public

Dantu Nandini Devi | https://www.vlsisystemdesign.com/

This is a model of a Freqency Divider. This model will contain a 4 bit number lines to select by...

iiitb_rc public

Kavya Agarwal | https://www.vlsisystemdesign.com/vsd-iat/

Ring Counter

mpw7 walkthrough public

Matt Venn

mpw7 walkthrough

Hyperspace-resubmission public

Vladimir Milovanović | www.novelic.com

A hybride parameterizable radar signal processing accelerator

iiitb_rtc public

BANDA ANUSHA | https://www.vlsisystemdesign.com/

Real-Time Clock

ppcpu public

Piotr Wegrzyn

Pipelined 16 bit cpu with custom architecture

RVcore Chip1 public

Kenji Kise | https://www.arch.cs.titech.ac.jp/

Design a five-stage pipelining processor of RISC-V RV32I

Patmos MPW7 public

Martin Schoeberl | https://github.com/os-chip-design/os-chip-design

The Patmos processor. A one-semester project with 12 students at the Technical University of...

Project-Yatsuhashi public

Yukidamayaki | analogmiko.com

RF Magic

ReRAM-Controller-MPW7 public

Po-Chun Huang | https://ece.umd.edu/

This project contains array of various sizes of 1T1R devices and a 1T1R 256x256 ReRAM module for...

64-Bit Adder public

Kerem Can Balı

64-Bit 2 Number - calculator

hehecore public

Yifei Zhu | https://rioslab.org/

We come from RIOS Lab, TsingHua university, we designed a 64-bit dual-issue, out-of-order RISC-V...

Swayambhu RISC processor public


RISC based procesor

test digital precheck public

Chithambara Moorthii J

test for precheck digital

In-memory-computing-SRAM public

Deepak verma | https://home.iitd.ac.in/

SRAM in memory computing : The project includes SRAM In Memory Computing Accelerator.

Test_pcheck public


Testing precheck

Rift2Fake public

Ruige Lee

This is a Fake Rift2Core. There is a LFSR and Multiplier in it!

In-memory-computing-RRAM public

Chithambara Moorthii J | https://home.iitd.ac.in/

The project includes RRAM In Memory Computing Accelerator, by researchers mentioned below under...

sequence detector public

RAVI KIRAN REDDY GOGIREDDY | https://www.iiitb.ac.in/. https://www.vlsisystemdesign.com/

detecting the sequence 10111.

crypto_aes128 public

Uriel Jaramillo Toral | https://unidad.gdl.cinvestav.mx/

AES128 project test

Bitcoin-Mining-Asic public

Constantine Mantas

This ASIC takes as an input the header of a Blockchain and simulates the bitcoin mining process.

Chaos Automaton public

Alex Goldstein

An array of "Chaos Cells" that pass data onto one another in a loop, allowing for modifications...

Riscduino-QCore(Q2) public

Dinesh Annayya

Riscduino is a Quad 32 bit RISC V based SOC design pin compatible to arduino platform and this...

iiitb_piso public

Raj kachhadiya | https://www.vlsisystemdesign.com/

parallel in serial out

toysram-mpw7 public

Bill Flynn | https://openpower.foundation

Custom array design and test site

PicoRio2 64bit... public

rios_mpw | http://rioslab.org

The PicoRioCPU2641300 device is a single core 64-bit general-purpose microcontroller based on...

Miranda FPGA MPW7 public

Alexander Monakhov

MPW7 attempt to tapeout our Miranda FPGA. Increased density

Mixed-Signal-SoC-... public

Sepideh Asgari

Nanopore-based DNA sequencing is a unique, scalable technology, utilized to identify nucleotides...

4 bit Ring Counter public

Ramya Suriyarani | https://www.vlsisystemdesign.com/vsd-iat/

Ring Counter

A2P public

Bill Flynn | git.openpower.foundation

A VexRiscv core conversion to PPC32

extraction_test_s... public

Andrew P. Lentvorski

Basic structures to validate new analog extraction methodology

iiitb_icg public

Dantu Nandini Devi | https://www.vlsisystemdesign.com/vsd-iat/


RISC-V CPU public

Steve Goldsmith | https://aurifexlabs.com

It's a simple risc-v cpu

Leros public

Martin Schoeberl | https://github.com/leros-dev

The open-source Leros processor

PWM generator public

Pranav Vajreshwari | vsdiat.com

A physical implementation of a digital PWM generator. Designed with OpenLane.

YONGA-MCU public

Burak Aykenar | https://www.yongatek.com/

Yonga-MCU is a 32-bit RISCV-IMC instruction set compatible SoC design with peripherals like...

Microwatt MPW7 public

Anton Blanchard

Microwatt is a 64 bit OpenPOWER core written in VHDL. It includes an IEEE 754 double-precision...

iiitb_sdm public

Ajaykumar | https://www.iiitb.ac.in/

Sequence detector

RISC-V Single Cycle... public

Garrett C Botkin

First attempt at creating a RISC-V Single Cycle Core. Known issues are listed in the GitHub read me.

MPW6_resubmission public

Janani Aravind

Mitigating faults in digital designs using RHBD technique

iiitb_pwm_gen public

Gopala Krishna Reddy Sanampudi | https://www.iiitb.ac.in/

This project simulates the designed Pulse Width Modulated Wave Generator with Variable Duty...

iiitb_piso public

Mahati Basavaraju | https://www.vlsisystemdesign.com/

4-bit Parallel In Serial Out Shift Register

Zero to ASIC... public

Matt Venn | https://zerotoasiccourse.com

Zero to ASIC course group submission MPW7. We take all the designs from people on the course and...

Trainable NN public

Tamas Hubai

Neural network with on-chip training

Enhanced Chaotic... public

Parker Hardy | https://bemosc.olemiss.edu/

Two general frameworks called NLCS and FPCS are developed for building robust chaotic system...

iiitb_sd public

Anshul Madurwar | https://www.vlsisystemdesign.com/

This project simulates the design of a Sequence Detector built using the MOORE FSM logic. We can...

SRAMTestVehicleG3 public

Staf Verhaegen

Iteration on SRAM test vehicle that failed to be selected for MPW5 and MPW6

First Silicon (MPW-7) public



RhythmIC public

Abhinav Uppal | https://isn.ucsd.edu/courses/beng207/

Switched-cap based wavelet processor in sky130B.

Nanofabrication... public

Mehdi Saligane

Test Structures for NIST's Nanofabrication Project

Leaf-(mpw7) public

Daniel Santos

Leaf is a small 32-bit RISC core for simple applications.

demo_mpw_project public

Tanishq E


TinyTapeout public

Matt Venn | https://tinytapeout.com

Test to put 500 100x100um designs onto one chip. More info at https://tinytapeout.com

Open SubGHz public

Adan Kvitschal | moduhub.com

This project aims to provide basic blocks to build a low-power, low-cost RF interface capable of...

RNG based on a... public

Kaya Demir

A random number generator that uses the chaotic signals from a figaro based ring oscillator to...

TopmetalSe-DPS public

Xiaochen Ni | https://www.npl.washington.edu/

The TopmetalSe is a pixelated charge sensor in the Skywater 130nm process, designed for the...

alu public

AASHISH TIWARY | https://www.iiitb.ac.in/

The alu unit is being designed for handling the arithmetic and logical processes of the processor.

WARP-V public

Ali Imran

WARP-V is an open-source CPU core generator written in TL-Verilog with support for RISC-V and...

sram public

Chithambara Moorthii J

testing sram design in precheck

mpw-7-test public

Jeff DiCorpo

Test project for MPW-7

10b ADC and... public

Christoph Weiser

10b SAR-ADC, Bandgap reference, Testbuffer, Clock generator, LDO, Bias Network. Improved version...

Rift2Go_2310_Sky130_MPW7 public

Ruige Lee

This is a simple version of Rift2Core. Rift2310 has a very small L2 cache, L1 Cache, no L2 TLB,...

Marmot RISC-V... public

Shumpei Kawasaki | www.swhwc.com

Increased features (plus 8KB D-Cache and 3ch PWM)and improved clocking (25MHz > 50MHz) by...

neoPix public

Prasad Pandit

Implementation of one wire protocol which controls neoPixel LEDs. The project is to validate...

RTCClock public

Filippo Carastro

RTCClock is an open source IP used to have a clock inside microcontroller for project that need...

OTAinfo... public

Akshaykumar Mehta | otainfo.com

A step towards making silicon to application layer operate in discrete boxed functions.

Linux capable SoC public

Mohamed Ali Younis

This is a graduation project in ASU 22 building Linux-capable RISCV core integrated with OpenPiton SoC

test public

Matt Venn


Observability Project public

Akshaykumar Mehta | otainfo.com

A step towards making silicon to application layer operate in discrete boxed functions.

hehecore_resubmission public

Yifei Zhu | https://rioslab.org/

We come from RIOS Lab, TsingHua university, we designed a 64-bit dual-issue, out-of-order RISC-V...


Chithambara Moorthii J

In Memory computing RRAM accelerator.

Braun public

Narsepalli Pradyumna

Braun Multiplier