Aloke Das
This is simple microprocessor. Instruction Set Architecture (ISA). The data bus is 16 bits wide....
Sam Lim
An initial attempt to create a Test chip
Vijayan Krishnan | https://www.chipwaretechnologies.com/
The openGFX430 is a synthesizable Graphic controller written in Verilog and tailored for the...
Luca Pezzarossa
Test of new patmos
Leo Moser | https://www.semify-eda.com
A generic waveform generator divided into stimulus and driver units that can be arbitrarily...
Soumil Jain | https://isn.ucsd.edu/courses/beng207/
ReRAM 16x16 array characterisation, including forming, incremental set and reset, and parallel...
Ian Zhang
Systolic Array is a classical architecture that is recently revitalized among Neural Network...
Nguyen Dao
This project demonstrates a customized Rocket Chip SoC, generated from Chipyard. The SoC is...
Dinesh Annayya
Arduino pin compatible Single RISCV 32 Bit core Project
Po-Chun Huang | https://ece.umd.edu/
This project contains array of various sizes of 1T1R devices and a 1T1R 256x256 ReRAM module for...
Simon Waid | https://www.oeaw.ac.at/en/hephy/
This is a simple analog fronted for particle detection. The user may attach a particle detector...
Abdullah YILDIZ | https://yongatek.com/
YONGA-CAN Controller is a partial implementation of CAN 2.0B standard.
Mathis Salmen
SoomRV is a simple superscalar Out-of-Order RISC-V microprocessor. It can execute 4 Instructions...
Allen Boston | https://github.com/lnis-uofu
User project wrapper includes the PMU version 3, SOFA 2x2 FPGA generated using OpenFPGA, and...
Dinesh Annayya
Riscduino is a Dual 32 bit RISC V based SOC design pin compatible to arduino platform and this...
Tiago Silva
This project contains a digital IIR biquad filter. Adapted from:...
RECEP GÜNAY
Cryptographically Secure RNG Design. (MPW6 resubmission)
Zexi Liu | https://www.cmu.edu/
This project aims to build multi-purpose characterization on-chip instruments using the...
Gopala Krishna Reddy Sanampudi | https://www.iiitb.ac.in/
Pulse Width Modulation is a famous technique used to create modulated electronic pulses of the...
Nguyen Dao
This project demonstrates open source eFPGA generated by FABulous. This version is to support...
Carl L Brando | https://umd.edu/
We have a 2x2 1T1R ReRam structure and a C4 Filter as well as some other supporting analog...
Maurya Patel | https://www.vlsisystemdesign.com/
A Traffic light controller made using sky130 technology node. Traffic lights are signaling...
Vinay Rayapati | https://www.vlsisystemdesign.com , https://www.iiitb.ac.in
This project provides an insight into the working of a few important instructions of the...
Wouter van Verre
An accelerator core for finding binary sequence with low autocorellation values
Debangana Mukherjee | https://www.vlsisystemdesign.com/vsd-iat/
4-bit Universal Shift Register
Joshua Stevens
A phased PWM controller for micro motor control
Marwan Abbas
SPM example user project
Jure Vreča | https://github.com/jurevreca12/rvj1-caravel-soc-mpw7
A simple SoC using the custom riscv-jedro-1 processor design.
김태현 | https://github.com/thkim2031
In this chip there are four macros : 1. b-float FMA (16bit multiplication and 32bit...
Binoy B
Implementation of an 8x64 memory array
Larry Pearlstein | http://pearlstein.pages.tcnj.edu
Retarget FPGAs to standard cell.
Yashwant Moses | vsdiat.com
Booth's Multiplier is based on Booth's Multiplication Algorithm. It proposes an efficient way...
Zexi Liu | www.cmu.edu
SKYWATER Lab-on-chip IC resubmission. This project aims to build multi-purpose characterization...
Dantu Nandini Devi | https://www.vlsisystemdesign.com/
This is a model of a Freqency Divider. This model will contain a 4 bit number lines to select by...
Matt Venn
mpw7 walkthrough
Vladimir Milovanović | www.novelic.com
A hybride parameterizable radar signal processing accelerator
Piotr Wegrzyn
Pipelined 16 bit cpu with custom architecture
Kenji Kise | https://www.arch.cs.titech.ac.jp/
Design a five-stage pipelining processor of RISC-V RV32I
Martin Schoeberl | https://github.com/os-chip-design/os-chip-design
The Patmos processor. A one-semester project with 12 students at the Technical University of...
Po-Chun Huang | https://ece.umd.edu/
This project contains array of various sizes of 1T1R devices and a 1T1R 256x256 ReRAM module for...
Kerem Can Balı
64-Bit 2 Number - calculator
Yifei Zhu | https://rioslab.org/
We come from RIOS Lab, TsingHua university, we designed a 64-bit dual-issue, out-of-order RISC-V...
MUKUL LOKHANDE
RISC based procesor
Chithambara Moorthii J
test for precheck digital
Deepak verma | https://home.iitd.ac.in/
SRAM in memory computing : The project includes SRAM In Memory Computing Accelerator.
KSHITIZ TYAGI
Testing precheck
Ruige Lee
This is a Fake Rift2Core. There is a LFSR and Multiplier in it!
Chithambara Moorthii J | https://home.iitd.ac.in/
The project includes RRAM In Memory Computing Accelerator, by researchers mentioned below under...
RAVI KIRAN REDDY GOGIREDDY | https://www.iiitb.ac.in/. https://www.vlsisystemdesign.com/
detecting the sequence 10111.
Constantine Mantas
This ASIC takes as an input the header of a Blockchain and simulates the bitcoin mining process.
Alex Goldstein
An array of "Chaos Cells" that pass data onto one another in a loop, allowing for modifications...
Dinesh Annayya
Riscduino is a Quad 32 bit RISC V based SOC design pin compatible to arduino platform and this...
rios_mpw | http://rioslab.org
The PicoRioCPU2641300 device is a single core 64-bit general-purpose microcontroller based on...
Alexander Monakhov
MPW7 attempt to tapeout our Miranda FPGA. Increased density
Sepideh Asgari
Nanopore-based DNA sequencing is a unique, scalable technology, utilized to identify nucleotides...
Andrew P. Lentvorski
Basic structures to validate new analog extraction methodology
Pranav Vajreshwari | vsdiat.com
A physical implementation of a digital PWM generator. Designed with OpenLane.
Burak Aykenar | https://www.yongatek.com/
Yonga-MCU is a 32-bit RISCV-IMC instruction set compatible SoC design with peripherals like...
Anton Blanchard
Microwatt is a 64 bit OpenPOWER core written in VHDL. It includes an IEEE 754 double-precision...
Garrett C Botkin
First attempt at creating a RISC-V Single Cycle Core. Known issues are listed in the GitHub read me.
Janani Aravind
Mitigating faults in digital designs using RHBD technique
Gopala Krishna Reddy Sanampudi | https://www.iiitb.ac.in/
This project simulates the designed Pulse Width Modulated Wave Generator with Variable Duty...
Mahati Basavaraju | https://www.vlsisystemdesign.com/
4-bit Parallel In Serial Out Shift Register
Matt Venn | https://zerotoasiccourse.com
Zero to ASIC course group submission MPW7. We take all the designs from people on the course and...
Tamas Hubai
Neural network with on-chip training
Parker Hardy | https://bemosc.olemiss.edu/
Two general frameworks called NLCS and FPCS are developed for building robust chaotic system...
Anshul Madurwar | https://www.vlsisystemdesign.com/
This project simulates the design of a Sequence Detector built using the MOORE FSM logic. We can...
Staf Verhaegen
Iteration on SRAM test vehicle that failed to be selected for MPW5 and MPW6
Horace
Erm
Abhinav Uppal | https://isn.ucsd.edu/courses/beng207/
Switched-cap based wavelet processor in sky130B.
Mehdi Saligane
Test Structures for NIST's Nanofabrication Project
Daniel Santos
Leaf is a small 32-bit RISC core for simple applications.
Tanishq E
Demo
Matt Venn | https://tinytapeout.com
Test to put 500 100x100um designs onto one chip. More info at https://tinytapeout.com
Adan Kvitschal | moduhub.com
This project aims to provide basic blocks to build a low-power, low-cost RF interface capable of...
Kaya Demir
A random number generator that uses the chaotic signals from a figaro based ring oscillator to...
Xiaochen Ni | https://www.npl.washington.edu/
The TopmetalSe is a pixelated charge sensor in the Skywater 130nm process, designed for the...
AASHISH TIWARY | https://www.iiitb.ac.in/
The alu unit is being designed for handling the arithmetic and logical processes of the processor.
Ali Imran
WARP-V is an open-source CPU core generator written in TL-Verilog with support for RISC-V and...
Chithambara Moorthii J
testing sram design in precheck
Jeff DiCorpo
Test project for MPW-7
Christoph Weiser
10b SAR-ADC, Bandgap reference, Testbuffer, Clock generator, LDO, Bias Network. Improved version...
Ruige Lee
This is a simple version of Rift2Core. Rift2310 has a very small L2 cache, L1 Cache, no L2 TLB,...
Shumpei Kawasaki | www.swhwc.com
Increased features (plus 8KB D-Cache and 3ch PWM）and improved clocking (25MHz > 50MHz) by...
Prasad Pandit
Implementation of one wire protocol which controls neoPixel LEDs. The project is to validate...
Filippo Carastro
RTCClock is an open source IP used to have a clock inside microcontroller for project that need...
Akshaykumar Mehta | otainfo.com
A step towards making silicon to application layer operate in discrete boxed functions.
Mohamed Ali Younis
This is a graduation project in ASU 22 building Linux-capable RISCV core integrated with OpenPiton SoC
Matt Venn
test
Akshaykumar Mehta | otainfo.com
A step towards making silicon to application layer operate in discrete boxed functions.
Yifei Zhu | https://rioslab.org/
We come from RIOS Lab, TsingHua university, we designed a 64-bit dual-issue, out-of-order RISC-V...
Chithambara Moorthii J
In Memory computing RRAM accelerator.
Narsepalli Pradyumna
Braun Multiplier