The booming open-source EDA ecosystem brings transparency and reproducibility to VLSI field, lowering the threshold for CPU design. To facilitate a reliable chip manufacturing flow and prepare for future agile development, we constructed a full-stack design methodology for modern processors in an open-source mode based on our experience in the efabless MPW-7 shuttle . We developed a 64-bit dual-issue, out-of-order RISC-V microprocessor “GreenRio”, and completed the back-end process of “RTL-Verification-GDS-Signoff” purely depending on the open-source EDA toolchain. In this paper, we analyzed multiple open-source EDA tools from ASIC front-end to back-end. We also proposed some innovations and adaptations based on existing open resources. Moreover, we compared commercial and open-source EDA tools from a modern processor design perspective, with the limitations and future optimizations of the open-source tool summarized. We hope our methodology can help shed new light upon agile modern architecture development.
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We come from RIOS Lab, TsingHua university, we designed a 64-bit dual-issue, out-of-order RISC-V processor, the url below is for the MPW7 resubmission, and the original one is https://github.com/b224hisl/rioschip.git