Tomas Choi | https://c2s2.engineering.cornell.edu/
Digital test chip for C2S2 team.
H.S.Thakar_PICT EnTC | www.pict.edu
We have Functionally verified VeriLog Model for 8-bit TRELLIS ENCODER. We also have the GDS-II...
Tomas Choi | https://c2s2.engineering.cornell.edu/
This is the project for C2S2's digital chip.
Tomas Choi | https://c2s2.engineering.cornell.edu/
This is the project for C2S2's Analog test chip.
Xinze Wang
Use AI to create a cpu core
Uri Shaked | https://tinytapeout.com/
Visit https://tinytapeout.com for more information on the project and how to get involved
Asma Mohsin
MPC, or Model Predictive Control, is a control strategy that utilizes mathematical models to...
Asma Mohsin
MPC, or Model Predictive Control, is a control strategy that utilizes mathematical models to...
xinze wang
A RISC-V five-level pipeline CPU core dominated by GPT-4
Efe Bayrakçeken
Do you need a really inefficent vga controller that was written by ai that only can do black and...
Alex P James
Verilog implementation of Sigmoid function using Zhang approximation
Anthony Kung | http://anth.dev
This project serves as an aid to the Raspberry Pi by providing an on-device image classification...
David Lanzendörfer
It's a proof of concept for an open source AI accelerator. So far, matrix multiplication and...
Mahnoor Ismail | https://github.com/merledu
This is a minimal Neural Processing Unit, developed purely by using prompt to GPT-4. It contains...
David Yang
RF Receiver front-end for WiFi 6 (5.925 GHz).
Anish Singhani
Student-submitted designs in the 18-224/624 Intro to Open Source Chip Design class at Carnegie...
Hammond Pearce
An accumulator-based 8-bit microarchitecture designed via GPT-4 conversations.
SUMANTO KAR | https://esim.fossee.in/ https://www.vlsisystemdesign.com/
"In the context of the Bloom Filter Counter, we adapt the Bloom filter concept to create a...
Tomas Choi | https://c2s2.engineering.cornell.edu/
This is the project for C2S2's digital chip.
Uri Shaked | https://tinytapeout.com/
Visit https://tinytapeout.com for more information on the project and how to get involved
Bassant Hassan
Includes 3 different IPs; PSRAM controller, timer, and UART
Dinesh Annayya
Riscduino is a Dual 32 bit RISC V based SOC design pin compatible to arduino platform and this...
Bassant Hassan
A test chip including three 3.3 V to 1.8 V, logic-controlled LDOs
Bassant Hassan
AES accelerator example connected on the WB bus
Jeff DiCorpo
Caravel User Project for CI2306
Mustafa Khatri
This is a very small part of my FYP, working under the Mentorship of Prof. Dr. Attiya Baqai, as...