# QTCore-C1
*Author*: Hammond Pearce
*Description*: An accumulator-based 8-bit microarchitecture designed
via GPT-4 conversations.
## How it works and design motivation
The QTCore-C1 is a comprehensive accumulator-based 8-bit microarchitecture.
It is a Von Neumann design (shared data and instruction memory).
Probably the most interesting thing about this design is that all
functional Verilog beyond the top level wrapper was written by GPT-4,
i.e. not a human!
The author (Hammond Pearce) developed with GPT-4 first the ISA,
then the processor, fully conversationally. Hammond wrote the test-benches
to validate the design, and then had the
appropriate back-and-forth with GPT-4 to have it fix all bugs.
For your interest, we provide all conversation logs in the project
repository under the `/AI_generation_information` directory.
This processor is based on the ideas undertaken in the
[Chip-Chat](https://arxiv.org/abs/2305.13243) research project,
where Dr. Pearce shephereded GPT-4 to design a basic processor,
the QTCore-A1. This was a very constrained design as it needed
to fit within the requirements of Tiny Tapeout 3, meaning it had a
lot of spatial (less than 20 bytes of instruction/data memory!) and
functionality constraints (basically no peripherals).
The QTCore-C1 is a much more comprehensive design which was made
for Efabless's first [AI generated Design Contest](https://efabless.com/ai-generated-design-contest).
Targeted to Caravel, it has a lot more space available to it than with
Tiny Tapeout. As such, it has a full 256 bytes of instruction and
data memory, as well as 8-bit I/O ports, as an internal 16-bit timer,
and even memory execution protection across 16-byte segments!
Due to these expanded properties, it is a much more complex
design with a lot more Verilog code as well as a much more
comprehensive ISA, and the two processors, although sharing some
similarities, are broadly incompatible.
*What could this be used for?* Practically, you could imagine a little
co-processor like this being used for predictable-time I/O state
machines, similar to the RP2040's PIO. It helps that this design is
quite small, and could be easily replicated many times on a single die.
It also has 8-bit I/O, an interrupt output, a timer, and signal I/O to
the larger Caravel processor, making it potentially useful for many
applications.
*Why make this design instead of something like RISC-V?*: There are many
implementations of open-source processors for ISAs like RISC-V and MIPS.
The problem is, that means GPT-4 has seen these designs during training.
For Efabless's generative AI contest (and the earlier Chip-Chat work),
I didn't want to explore simply the capabilities of GPT-4 to emit data
it has trained over - rather, I wanted to see how they performed when
making something more novel. As such, I shephereded the models into
making wholly new designs, with strange ISAs quite different to what
is available in the open-source literature.
*A security experiment*: The memory execution protection scheme was
added primarily to test to see if ChatGPT-4 would then 'knowingly' create
a backdoor, which it politely did (see Conversation C18 in the QTCore-C1
logs). This is a very interesting result, as it shows that GPT-4 is capable
of both 'understanding' the concept of security, and that it is also capable
of creating a backdoor to circumvent it.
Please view more details in the full project README on GitHub!
