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MPW-2 Shuttle Projects

FABulous_Sky public

Nguyen Dao

Demonstration of the Fabulous FPGA design flow using the Skywater 130 process. The design...

General_Purpose_B... public

Anmol Purty | https://www.vlsisystemdesign.com/

A General Purpose Bandgap Reference IP block that generates constant voltage at output, which is...

uqab public

Waleed Waseem

uqab is an SoC.

azadi_soc_ibex public

Zeeshan Rafique | https://www.linkedin.com/company/merluit

Azadi is an SoC with a 32-bit RISC-V signal core extended version of ibex we named it "buraq",...

Fast GCD for... public

Kavya Sreedhar

Computes the Bezout coefficients associated with 1024 bit numbers with a GCD of 1.

8x_PLL_Clock_Multiplier public

Subham Mohapatra | https://www.vlsisystemdesign.com/

8x PLL Clock Multiplier. Input frequency ranges from 5MHz to 12MHz and output frequency is from...

space_shuttle public

Ahmad Nofal

small summary never hurts

Test Chip 0 -... public

Russell Friesenhahn | https://www.utexas.edu/

This project demonstrates a butterfly for an FFT with options to receive data from an external...

Libre-SOC Crypto-Router public

Luke Leighton | http://libre-soc.org

Libre-SOC is an entirely Libre-licensed SoC based on the OpenPOWER v3.0 ISA. Layout is in...

clusterv_soc_mpw2 public

Matthew Ballance

Quad-core RISC-V SoC with on-chip memory and peripherals

OsciBear public

Dan Fritchman

Berkeley student-designed wireless SoC, featuring a RISC-V Rocket processor, hardware AES...

Caravel_FPU public

Komal Javed | https://lampromellon.com/

Caravel_FPU integrates floating point unit with Caravel Core. It is capable of doing floating...

caravel_dsc public

Raj Babu

Caravel Harness based Digital Signal Controller for Embedded Control applications , the user...

SHA1 engine public

Konrad Rzeszutek Wilk

The SHA1 engine, while not the most secure nowadays is still used by git commits and TPM PCR...

Space_Shuttle public

Iván Rodríguez Ferrández | https://www.bsc.es

The main goal of this project is to assess the reliability of the SkyWater 130nm manufacturing...

FuseRISC public

Andrew Attwood | https://github.com/andrewattwood/fuserisc.git

FuseRISC will demonstrate the benefits of the tight coupling of RISC-V cores and eFPGA fabric...

Bandgap_Reference_Design public

Swarup Pulujkar | https://www.vlsisystemdesign.com

A Bandgap Reference Circuit To Generate A Constant Voltage Output That Is Insensitive To...

darkriscv in openlane public

Bhawandeep Singh

The project is a realization of darkriscv processor using openlane and skywater pdk. It has a...

AutomaticStandard... public

Philipp Gühring | https://libresilicon.com/

At Libresilicon we have been working for several years on making chipdesign and production...

io_expander public

Siva Prasad

A gpio expander for the caravel harness to realize a small microcontroller

Lexicon public


This Is A Machine-Mode (M-Mode) Only, 32-Bit Cpu Small Core Which Supports Risc-V’s Integer (I),...

YiFive (Risc V Based... public

Dinesh Annayya

32 Bit Risc SOC Design with Quad SPI , 8 bit SDRAM Controller , UART, I2C Master and USB 1.1 Host

Comparator VCO... public

Malay Das | https://www.vlsisystemdesign.com/

Comparator at 3v3 Supply Voltage Voltage Controlled Oscillator with 7 stage ring oscillator...

multi project harness... public

Matt Venn

saves space on the shuttle by aggregating up to 16 designs in one submission

Hilas Analog... public

Barry Muldrey | https://gitlab.com/um-ece/ftl-lab/hilas

Analog std cells and test structures for audio processing and analog computing

AXI DMA using Spinal... public

Pu Wang

This is a DMA controller with AMBA AXI4 interface. This DMA controller is part of an ongoing...

caravel_analog_fulgor public

Diego Hernando | http://www.fundacionfulgor.org.ar/sitio/index.php

Analog test chip with master's thesis prototypes: - 1GHz Current Starved VCO - Residual...

BrqRV_EB1 public

Micro Electronics Research LAB (MERL)

BrqRV EB1 is a machine-mode (M-mode) only, 32-bit CPU small core which supports RISC-V’s integer...

Analog Neuron public

Lakshmi S

Analog implementation of the artificial Neuron used in neural networks. Implements the network...

Columbus public

Thomas Stanway-Mayers

Analog Test Chip Consisting of the following: LDO, Load Switch, Bandgap Reference, and an OpAmp

YONGA-LZ4 Decoder public

Abdullah YILDIZ | https://yongatek.com/

YONGA-LZ4 Decoder Is An Implementation Of The Decoder Of The Popular Lz4 Compression Algorithm.

RenML public

Tayyeb Mahmood | https://www.renzym.com/

A small, Convolutional Neural Network Accelerator on a wishbone slave for Raven Core in Caravel SoC.

Potentiometric_Di... public

S Skandha Deepsita | https://www.vlsisystemdesign.com/

The project aims to design a 10-bit Potentiometric Digital to Analog Converter(DAC). The target...

Amsat TXRX IC MPW2 public

Thomas Parry | https://github.com/yrrapt/amsat_txrx_ic

This step in the development and prototyping of the Amateur Radio Satellite Transceiver project...

Digital PLL public

Amro Tork | https://mabrains.com

Integer Digitall PLL + LDO + Bandgap + Error Amplifier Design

Wishbone CAN public

Zachary Ellis

An implementation of a CAN bus controller as a wishbone peripheral for the open MPW shuttle

SOFA Plus FPGA public

Xifan Tang | https://github.com/lnis-uofu/SOFA.git

SOFA (Skywater Opensource FPGAs) are a series of open-source FPGA IPs using the open-source...

sram_abstraction_trial_1 public

Ahmad Nofal

just a trial

UCSC OpenRAM Test Chip public

Matthew Guthaus | https://vlsida.soe.ucsc.edu

Test chip for single and dual port memories created by OpenRAM.

Opencryo_testchip public

Francisco Brito Filho

NMOS and PMOS array, ring oscillator and inductor for cryogenic characterization.

Kasirgalabs UART public

Iremnur Colak | https://www.kasirgalabs.com/en/

Simple UART controller

caravel_dsp2 public

Jayakumar Janarthanam

DSP Functions

VSD SRAM MPW2 public

Shon Taware | https://vlsisystemdesign.com/

Design of SRAM cell array with a configuration of 1.8 V operating voltage using Google SkyWater...

OpenFASOC public

Mehdi Saligane

This testchip is a demonstrator of our automated analog generators within an SoC implementation....

EE272B test project public

Daniel Stanley

I don't intend to tape this out, but I am mentoring some other projects and would like to go...

Alperens SOC public

Alperen Bolat

Custom Risc V processor design

Noise-Shaping TDC public

Victor PM

High-resolution time-to-digital converter (TDC) for accurate time measurement, applicable to...

10_bit_potentiometric_DAC public

Sameer S Durgoji | https://www.vlsisystemdesign.com/

Design of a 10 Bit Potentiometric Digital to Analog Converter with 3.3V analog voltage, 1.8V...

Caravel-Sermo public

Tayyeb Mahmood | https://uet.edu.pk/

The project implements a PID controller using encoder feedback and single channel of PWM output...

Subservient SOC public

Priyanka Dutta

SERV is a bit-serial CPU which means that the internal datapath is one bit wide and it is the...

Caravel_Multi_encoder-v1 public

Manikandan Nagarajan

Multipurpose integrated encoder

Subservient public

Klas Nordmark

ASIC adaption of SERV, the award-winning bit serial RISC-V processor.

Caravel_Multi_encoder public

Manikandan Nagarajan | https://www.sastra.edu/

Multi purpose integrated encoder

DVSoC public

Dilip Vasudevan


dummt public

wajeh ul hasan


vlsi-sky130-analo... public

Mariano Alvira

First try at open mpw: simple analog circuits

Open PMIC public

Weston Braun

A current mode buck converter with an analog controller to derive the 1.8V logic voltage from...