Nguyen Dao
Demonstration of the Fabulous FPGA design flow using the Skywater 130 process. The design...
Anmol Purty | https://www.vlsisystemdesign.com/
A General Purpose Bandgap Reference IP block that generates constant voltage at output, which is...
Waleed Waseem
uqab is an SoC.
Zeeshan Rafique | https://www.linkedin.com/company/merluit
Azadi is an SoC with a 32-bit RISC-V signal core extended version of ibex we named it "buraq",...
Kavya Sreedhar
Computes the Bezout coefficients associated with 1024 bit numbers with a GCD of 1.
Subham Mohapatra | https://www.vlsisystemdesign.com/
8x PLL Clock Multiplier. Input frequency ranges from 5MHz to 12MHz and output frequency is from...
Ahmad Nofal
small summary never hurts
Russell Friesenhahn | https://www.utexas.edu/
This project demonstrates a butterfly for an FFT with options to receive data from an external...
Luke Leighton | http://libre-soc.org
Libre-SOC is an entirely Libre-licensed SoC based on the OpenPOWER v3.0 ISA. Layout is in...
Matthew Ballance
Quad-core RISC-V SoC with on-chip memory and peripherals
Dan Fritchman
Berkeley student-designed wireless SoC, featuring a RISC-V Rocket processor, hardware AES...
Komal Javed | https://lampromellon.com/
Caravel_FPU integrates floating point unit with Caravel Core. It is capable of doing floating...
Raj Babu
Caravel Harness based Digital Signal Controller for Embedded Control applications , the user...
Konrad Rzeszutek Wilk
The SHA1 engine, while not the most secure nowadays is still used by git commits and TPM PCR...
Iván Rodríguez Ferrández | https://www.bsc.es
The main goal of this project is to assess the reliability of the SkyWater 130nm manufacturing...
Andrew Attwood | https://github.com/andrewattwood/fuserisc.git
FuseRISC will demonstrate the benefits of the tight coupling of RISC-V cores and eFPGA fabric...
Swarup Pulujkar | https://www.vlsisystemdesign.com
A Bandgap Reference Circuit To Generate A Constant Voltage Output That Is Insensitive To...
Bhawandeep Singh
The project is a realization of darkriscv processor using openlane and skywater pdk. It has a...
Philipp Gühring | https://libresilicon.com/
At Libresilicon we have been working for several years on making chipdesign and production...
Siva Prasad
A gpio expander for the caravel harness to realize a small microcontroller
Wajeh
This Is A Machine-Mode (M-Mode) Only, 32-Bit Cpu Small Core Which Supports Risc-V’s Integer (I),...
Dinesh Annayya
32 Bit Risc SOC Design with Quad SPI , 8 bit SDRAM Controller , UART, I2C Master and USB 1.1 Host
Malay Das | https://www.vlsisystemdesign.com/
Comparator at 3v3 Supply Voltage Voltage Controlled Oscillator with 7 stage ring oscillator...
Matt Venn
saves space on the shuttle by aggregating up to 16 designs in one submission
Barry Muldrey | https://gitlab.com/um-ece/ftl-lab/hilas
Analog std cells and test structures for audio processing and analog computing
Pu Wang
This is a DMA controller with AMBA AXI4 interface. This DMA controller is part of an ongoing...
Diego Hernando | http://www.fundacionfulgor.org.ar/sitio/index.php
Analog test chip with master's thesis prototypes: - 1GHz Current Starved VCO - Residual...
Micro Electronics Research LAB (MERL)
BrqRV EB1 is a machine-mode (M-mode) only, 32-bit CPU small core which supports RISC-V’s integer...
Lakshmi S
Analog implementation of the artificial Neuron used in neural networks. Implements the network...
Thomas Stanway-Mayers
Analog Test Chip Consisting of the following: LDO, Load Switch, Bandgap Reference, and an OpAmp
Abdullah YILDIZ | https://yongatek.com/
YONGA-LZ4 Decoder Is An Implementation Of The Decoder Of The Popular Lz4 Compression Algorithm.
Tayyeb Mahmood | https://www.renzym.com/
A small, Convolutional Neural Network Accelerator on a wishbone slave for Raven Core in Caravel SoC.
S Skandha Deepsita | https://www.vlsisystemdesign.com/
The project aims to design a 10-bit Potentiometric Digital to Analog Converter(DAC). The target...
Thomas Parry | https://github.com/yrrapt/amsat_txrx_ic
This step in the development and prototyping of the Amateur Radio Satellite Transceiver project...
Amro Tork | https://mabrains.com
Integer Digitall PLL + LDO + Bandgap + Error Amplifier Design
Zachary Ellis
An implementation of a CAN bus controller as a wishbone peripheral for the open MPW shuttle
Xifan Tang | https://github.com/lnis-uofu/SOFA.git
SOFA (Skywater Opensource FPGAs) are a series of open-source FPGA IPs using the open-source...
Ahmad Nofal
just a trial
Matthew Guthaus | https://vlsida.soe.ucsc.edu
Test chip for single and dual port memories created by OpenRAM.
Francisco Brito Filho
NMOS and PMOS array, ring oscillator and inductor for cryogenic characterization.
Jayakumar Janarthanam
DSP Functions
Shon Taware | https://vlsisystemdesign.com/
Design of SRAM cell array with a configuration of 1.8 V operating voltage using Google SkyWater...
Mehdi Saligane
This testchip is a demonstrator of our automated analog generators within an SoC implementation....
Daniel Stanley
I don't intend to tape this out, but I am mentoring some other projects and would like to go...
Alperen Bolat
Custom Risc V processor design
Sameer S Durgoji | https://www.vlsisystemdesign.com/
Design of a 10 Bit Potentiometric Digital to Analog Converter with 3.3V analog voltage, 1.8V...
Tayyeb Mahmood | https://uet.edu.pk/
The project implements a PID controller using encoder feedback and single channel of PWM output...
Priyanka Dutta
SERV is a bit-serial CPU which means that the internal datapath is one bit wide and it is the...
Manikandan Nagarajan
Multipurpose integrated encoder
Klas Nordmark
ASIC adaption of SERV, the award-winning bit serial RISC-V processor.
Manikandan Nagarajan | https://www.sastra.edu/
Multi purpose integrated encoder
Dilip Vasudevan
NAISoC
wajeh ul hasan
dummy
Mariano Alvira
First try at open mpw: simple analog circuits
Weston Braun
A current mode buck converter with an analog controller to derive the 1.8V logic voltage from...