This is a project to test a Standard Cell Library which is generated by the Libresilicon Standard Cell Library Generator. We generated a library of Standard Cells for the Sky130 process and this Project Places them inside Caravel so that you get a Chip which provides the functionality of the Standard Cell functions through the IOs and the built-In Logic Analyzer
At Libresilicon we have been working for several years on making chipdesign and production available to a wider public. One big step is now to automatically generate standard cell libraries just from the DRC rules and a given or even generated netlist.
sky130A