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WARP-V
public project
MPW-7   
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Owner
Ali Imran
Description

WARP-V is an open-source CPU core generator written in TL-Verilog with support for RISC-V and MIPS I. It is a demonstration and exploration vehicle for the flexibility that is possible using the emerging "transaction-level design" methodology. This submission involves a 4-stage RISC-V CPU version of WARP-V.

Category

processor

Process

sky130A