ABOUT

This project simulates the overlapping Moore Design for Sequence Detection where it toggles the output high for a certain input sequence. Over here the example is taken for 1010 for detection.

Working

• S0 (Reset or Zero State) Design of the Moore machine starts with the state S0 where we receive our first input signal. If we receive bit 1, we move to the next state of S1 or else we loop back to this state. We can also refer this state as the Reset State because every time we do not get the next desired input bit, we can always hop back to this state and restart the process.
• S1 (One State) We now have received the bit 1 and on receiving the bit 1 again, we will stay in this state, or else we move to next state of S2.
• S2 (OneZero State) We will advance to next state of S2 if we receive the bit 1 or else we will go back to state S0 because the sequence will be broken now.
• S3(OneZeroOne State) On receiving the bit 0, we will advance to next state or else we will move back to S1 state on receiving bit 1.
• S4 (OneZeroOneZero State) If we receive the bit 0, we will be going to state S0 as we can continue it for the next sequence or we will move to state S3 if we receive the bit 1. Irrespective of what bit is recieved in this state, output will trigger to high and then change corresponding to the inputs provided. Below shown is the wave file's output n testing the verilog code out against the testbench provided