This is chip is add-on to our Riscduino SCORE/DCORE/QCORE Chip set. As there are no free space in the previous chip and this chip will be host additional function like mac core, stepper motor and new feature as needed. This project uses only open source tool set for simulation,synthesis and backend tools. The SOC flow follow the openlane methodology and SOC environment is compatible with efabless/carvel methodology.
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* Open sourced under Apache-2.0 License (see LICENSE file) - unrestricted commercial use allowed.
* 100MB/10MB MAC core
* 4 pin Stepper Motor controller
* 8 x 2KB SRAM with MBIST controller
* Open-source tool set
* simulation - iverilog
* synthesis - yosys
* backend/sta - openlane tool set
* Verification suite provided.
This is chip is add-on to our Riscduino SCORE/DCORE/QCORE Chip set. As there are no free space in the previous chip and this chip will be host additional function like mac core, stepper motor and new feature as needed. This project uses only open source tool set for simulation,synthesis and backend tools. The SOC flow follow the openlane methodology and SOC environment is compatible with efabless/carvel methodology.
P0
sky130A