I. Introduction

Recently complexity has been shifting from hardware to software. 32-bit CPU cores themselves are becoming a commodity. To create anything useful, applications require complex software stacks. Traditional microcontroller chip vendors had their own compilers, IDE tools, software vocabulary and libraries. This lock-in approach works for small software but does not scale for IoT where network and security code are involved. For this reason, modern software developers require commodity tools like GCC and Clang rather than closed proprietary development tools. Microcontroller vendors need to join and actively participate in collaborative open source projects, which major players like Apple, Intel, ARM and recently also RISC-V have been doing.

One unique aspect of the SH architecture is that the ISA intellectual property ownership belongs to the public and its ability to run Linux with MMU and without MMU. Running Linux exposes the whole system to a lot of various use and test cases, which is difficult to achieve otherwise. At the same time, SH cores can be implemented in a compact and energy efficient manner. In general, 2-stage pipeline implementation achieves higher cycle performance than that of 5-stage pipeline for the same architecture. However, SH software support has been left behind recently, there are some deficits w.r.t. automatic compiler optimizations, which are crucial for modern software. Therefore, we will make the software support up to date, and show the latest evaluation result when we apply the presentation slides.

II. 2-Stage Pipeline SH-2 CPU

In 2015 we started designing the 2-stage pipeline SH-2 CPU in a clean room. We wrote the RTL of the CPU in System Verilog, used Perl script to assemble the micro-sequence description to System Verilog, simulated the RTL with Modelsim, and synthesized the RTL to Intel Max 10 FPGA device. Our design runs at 50MHz clock speed on the FPGA device. We believe the 2-stage-pipeline design is advantageous because (1) the branch instruction is faster due to shallow pipeline, (2) lower number of logic elements are consumed due to fewer pipeline stages, (3) the design achieves faster clock due to the simpler control and data paths, and (4) we could save the design resource due to the simplicity.

The SH-2 system has tightly coupled memories (TCMs), AHB and APB bus, interrupt controller, UART, PWM and ADC (from Max 10 FPGA). 

We conducted a sanity check by constructing real world application brushless DC motor control both sensored and sensorless. The SH-2 FPGA board is connected to a commercial inverter board which contains Gate Driver, coil driver MOSFETs and other circuits, and a Tsukasa TG55L 24V motor.

Fig. RISC CPU Area Breakdown: UMC 40nm Low Power Process

III. Implementation Results
Table 1 shows the implementation results of our 2-stage pipeline SH-2 CPU (H27604) on Intel Max 10 FPGA. The table also shows the comparison between our CPU and other similar CPUs. Aquarius is an open source CPU designed by Thorn Aitch and published in OpenCores [6]. Aquarius executes SH-2 instructions with 5-stage pipeline. SCR1 is also an open source CPU designed by Syntacore [8]. SCR1 executes RISC-V instructions with 2 to 4-stage pipeline. In Table 1, there are two versions of SCR1. SCR1(1) implements RV32IC ISA which includes 47 Integer (32bit encoding) instructions and 27 Compact (16bit encoding) instructions. SCR1(2) implements RV32IMC ISA which includes RV32IC + 8 Multiply/Divide instructions. As shown in Table 1, our 2-stage SH-2 CPU is the smallest and consumes only 4,655 logic cells and two 18x18 multipliers, while the clock frequency is comparable to other CPUs.

IV. Performance Evaluation
Fig. 1 shows the comparison of cycle performance between H27604 and Aquarius. EEMBC CoreMark [10] and various GCC versions and options were used for the comparison. As shown in Fig. 1, H27604 achieves 9% (avg.) better cycle performance than Aquarius.

V. Conclusion
We developed 2-stage-pipeline SH-2 CPU small and achieves good cycle performance. We implemented the CPU with some peripheral modules on Intel MAX 10 FPGA. The CPU consumes only 4,655 logic cells and can operate at 50MHz. We successfully demonstrate the FPGA system could control the brushless DC motor. The CPU consumes only 33KG of 40nm NVM process at 240MHz, and 20KG of 0.18um process at 80MHz. The CPU can be easily incorporated into FPGA and SoC for IoT, edge AI and robotic applications.

REFERENCE
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[10] EEMBC CoreMark Benchmark, https://www.eembc.org/coremark/about.php