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16bit-pipelined-R...
public project
MPW-8   
  • Developed a new Reduced Instruction Set with least possible no. of instructions in it such that the designed Processor can be used to implement almost any Function by combination of instructions
  • Using the concept of pipelining divided execution of instruction into three stages such that effectively one instruction is executed for every clock cycle
  • It is developed for understanding the micro-architecture and ways to develop a processor by students

There is no intention to copy or mimic any existing processor.

I would like to thank NSDCS lab IIT Indore ( https://sites.google.com/site/svishvakarma/home ), especially prof. Santosh K Vishvakarma and Radheshyam Sharma ( https://in.linkedin.com/in/radheshyam-sharma-37aa3713b ) for helping me and letting me know about this opportunity.

Organization URL

https://iiti.ac.in/

Description

Developed a 16bit processor having its own Reduced Instruction Set with least possible number of instructions in it such that the designed Processor can be used to implement almost any Function. The Developed IC can be used to understand mirco-architecture of a processor by students.

Version

2.0

Category

processor

Process

sky130A