Original project: https://platform.efabless.com/projects/12
The original goal of the PyFive project is to create a RISC-V based microcontroller with the ability to easily support CircuitPython.
For the first shuttle, we are starting small and verifying the USB core. The USB core is accompanied by simple audio and video output cores to fill in more of the user area.
Future plans are to create a full featured VexRiscV core with SRAMs once the OpenRAM support is released.
More info about PyFive: https://github.com/PyFive-RISC-V
Peripherals tests for future SoC targeting Micro/Circuit Python
1.0
usb
sky130A