This project makes additional memories accessible from Caravel  SoC (picorv32) via Wishbone bus:

1. Internal 1kB OpenRAM block (built in as macro)
2. HypeRAM memory (Cypress S27KL0641 8MB or similar) connected through HyperRAM memory driver (built in as macro)

The address space given to user project (0x3000_0000 - 0x30ff_ffff) is shared by these two blocks in following way:

Functionality implemented inside HyperRAM driver / limitations:

• working with wb_clk_i clock (external HyperRAM clock is two times smaller due to DDR)
• read and write to both memory and register space (inside HyperRAM chip)
• single 32 bit access to memory space (no burst)
• single 16 bit access to register space (inside HyperRAM chip)
• adjusting timings (tacc, tcsh, tpre, tpost and read timeout) possible via registers (accessible via Wishbone)
• fixed latency (1x/2x) or variable latency (according to RWDS signal state during CA phase) - configurable in register
• read timeout in case of external HyperRAM connection failure