This project makes additional memories accessible from Caravel SoC (picorv32) via Wishbone bus:
The address space given to user project (0x3000_0000 - 0x30ff_ffff) is shared by these two blocks in following way:
Functionality implemented inside HyperRAM driver / limitations:
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Project instantiates HyperRAM driver for external memory chip (8MB version) and additional OpenRAM 1kB block (32x256B). Both blocks are connected to Caravel SoC with Wishbone bus.
11/11/21 13:50:33 PST
12/28/21 07:41:12 PST