Efabless Logo
Crypto Accelerator v2
public project

This is a cryptography accelerator ASIC designed using the SKY130 process node. It includes key-limited hardware implementations of cores for AES128/AES256 and SHA256, as well as an experimental VGA-based game demo. The eventual goal of this project is to use it for embedded/IoT security applications.

This chip contains 4 major components:

  1. AES128/256 Accelerator

    • Optimized for balance between speed and area, can encrypt or decrypt a 16-byte block in ~20 cycles for AES128 or ~28 cycles for AES256
    • Supports both ECB and CBC modes (CBC is recommended because it is much more secure against block reuse attacks) with no performance penalty for using CBC


  1. SHA256 Accelerator

    • Can hash a single 512-bit block in ~66 cycles (and able to process multiple blocks immediately back-to-back, i.e. when hashing a large file)


  1. VGA Game Demo (experimental)

    • Original design was contributed by Ethan Polcyn (and then ported to run on the ASIC environment)
    • Consists of a small infinite side-scrolling jumping game (based on the Chromium Browser's "No internet"-game), playable using button input from one of the chip's I/O pins
    • Renders VGA video output at 640x480 through the chip's output pins


  1. Caravel harness/padframe
    • Contains a picorv32 CPU (which is used to interface with the rest of the cores through the Wishbone bus) and the padframe


project layout image
project layout image
Layout Image

SHA/AES accelerator and VGA graphics demo