The flexible 32-point DCT architecture was developed based on the Adaptic CORDIC (ACor) algorithm. Six different versions were implemented based on the number of DCT-point, i.e., 8-point (8p), 16-point (16p), and 32-point (32p), and the number of ACor stages, i.e., 2-Stage (2S) and 3-Stage (3S). The designs were written in Verilog HDL and were built on an FPGA. The advantages of ACor-based DCT are employing CORDIC and Twisted-Adder (TA), and TA was proved to have the minimum adder-delay while providing good accuracy outcomes. Therefore, it can achieve higher speed, low latency, and lower logic resources. The DCT core is open-source and free. This core can be applied in DSP systems, robotics, communication systems, video compression and decompression with H.265 standard. It was successully implemented on FPGA.
This is implementaion results on Stratix IV FPGA
The demo of compression and compression of Video RGB on FPGA
The layout of this core on Skywater 130nm
We make implementation of a flexible 32-point Discrete Cosine Transform (DCT). The architecture is based on the fixed-rotation adaptive COordinate Rotation DIgital Computer (CORDIC) algorithm.
acc
sky130A