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Floating_Point_Un...
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MPW-6   

Half Precision Floating Point Unit from MERL

This is the first ever Half Precision Floating Point Unit of IEEE-754 standard designed by undergraduate students of DHA Suffa University Pakistan. It support all the basic floating point instruction mention in RISC-V specs.

Directory Structure

+-- verlog                          #   User verilog Directory

    +-- rtl                         #   RTL

    +-- dv                          #   Design Verification

    +-- gl                          #   Gate Level Netlis

The Floating Point Unit Source Code is avaialable here

+-- verlog                               #   User verilog Directory

    +-- rtl                              #   RTL
    
    |       +-- user_project_wrapper.v       #   User Project Wrapper source file
    
    |       +-- user_proj_example.v          #   User Project Example source file
    
    |       +-- FPU                          #   Floating Point Unit folder

The Design Verification Testbench is available here

+-- verlog                               #   User verilog Directory

    +-- dv                               #   Design Verification
    
    +-- FPU_Half                         #   Design Test Directory
    
    +-- hex                              #   Hex files folder
    
    +-- asm                              #   Assmebly files folder

The synthesized netlist is present here: +-- verlog # User verilog Directory

    +-- gl                               #   Gate Level Netlis
    
    +-- user_project_wrapper.v       #   User Project Wrapper Netlist
    
    +-- user_proj_example.v          #   User Project Example Netlist

The hardened macros are placed here:

+-- def                                 #    def Directory
    
    +-- user_project_wrapper.def        #    User Project Wrapper def file

+-- lef                                 #    lef Directory

    +-- user_project_wrapper.lef        #    User Project Wrapper lef file

    +-- user_proj_example.lef           #    User Project Example lef file

+-- gds                                 #    gds Directory

    +-- user_project_wrapper.gdz.gz     #    User Project Wrapper gds

    +-- user_proj_example.gdz.gz        #    User Project Example gds

Testing of Design

Go to verilog/dv/FPU_Half/ directory

Set the GCC_PATH environment variable.

Set the PDK_PATH environment variable.

Copy the given program hex file into uart.hex.

run the make commad for RTL simulation

run the SIM=GL make command for netlist simulation

Note: Dont forget to add 00000010 and 00000FFF instruction in the end of the uart.hex to stop the uart transmission if you are using your own codes.

project layout image
project layout image
Layout Image
Owner
merl dsu
Organization URL

https://merledupk.org/

Description

This is the Floating point unit which supports the IEEE-754 Half Precision format. This FPU is designed by the undergraduate students of DHA Suffa University

Version

Version 1

Process

sky130A